Travelled to:3 × USA
Collaborated with:S.Sastry W.Chen J.Guo
Talks about:circuit (2) analysi (2) combin (2) time (2) test (2) distribut (1) silicon (1) process (1) coverag (1) random (1)
Person: Amitava Majumdar
DBLP: Majumdar:Amitava
Contributed to:
200619921991Wrote 3 papers:
- DAC-2006-MajumdarCG #analysis #validation
- Hold time validation on silicon and the relevance of hazards in timing analysis (AM, WYC, JG), pp. 326–331.
- DAC-1992-MajumdarS #fault #on the #random testing #testing
- On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits (AM, SS), pp. 341–346.
- DAC-1991-SastryM #analysis #branch #process
- A Branching Process Model for Observability Analysis of Combinational Circuits (SS, AM), pp. 452–457.