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Travelled to:
1 × USA
Collaborated with:
J.P.Hayes
Talks about:
dimension (1) generat (1) layout (1) optim (1) cmos (1) clip (1) cell (1) two (1)

Person: Avaneendra Gupta

DBLP DBLP: Gupta:Avaneendra

Contributed to:

DAC 19971997

Wrote 1 papers:

DAC-1997-GuptaH #2d #generative #layout #named #optimisation
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells (AG, JPH), pp. 452–455.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.