BibSLEIGH — layout tag

layout

layout

Tag #layout

497 papers:

FM-2019-LutebergetJS #capacity #specification #synthesis: Synthesis of Railway Signaling Layout from Local Capacity Specifications (BL, CJ, MS), pp. 121–137.
OOPSLA-2019-PanchekhaETK #composition #verification #web: Modular verification of web page layout (PP, MDE, ZT, SK), p. 26.
ASE-2019-YuF0Z0 #automation #image #mobile #named #platform #recognition #testing: LIRAT: Layout and Image Recognition Driving Automated Mobile Testing of Cross-Platform (SY, CF, YF0, WZ, ZC0), pp. 1066–1069.
ESEC-FSE-2019-WangXLLLQLL #memory management: Locating vulnerabilities in binaries via memory layout recovering (HW, XX, SWL, YL0, YL, SQ, YL0, TL0), pp. 718–728.
GPCE-2019-CronburgG #in memory #memory management #named: Floorplan: spatial layout in memory management systems (KC, SZG), pp. 81–93.
CC-2019-LavaeeCD #interprocedural #named #optimisation: Codestitcher: inter-procedural basic block layout optimization (RL, JC, CD), pp. 65–75.
CGO-2019-AgaA #named #runtime #stack: Smokestack: Thwarting DOP Attacks with Runtime Stack Layout Randomization (MTA, TMA), pp. 26–36.
ICST-2019-AlameerCH #constraints: Efficiently Repairing Internationalization Presentation Failures by Solving Layout Constraints (AA, PTC, WGJH), pp. 172–182.
ICST-2019-AlthomaliKM #automation #verification #visual notation #web: Automatic Visual Verification of Layout Failures in Responsively Designed Web Pages (IA, GMK, PM), pp. 183–193.
ICPR-2018-LinHLC #estimation #image: Indoor Scene Layout Estimation from a Single Image (HJL, SWH, SHL, CKC), pp. 842–847.
OOPSLA-2018-BielikFV #android #relational #robust #synthesis: Robust relational layout synthesis from examples for Android (PB, MF, MTV), p. 29.
PLDI-2018-PanchekhaGETK #verification #web: Verifying that web pages have accessible layout (PP, ATG, MDE, ZT, SK), pp. 1–14.
CASE-2018-HaoQ #automation #problem: Solving Unequal-Area Facility Layout Problems with Orbits in Fully Automatic System (XH, MQ), pp. 1183–1188.
CASE-2018-YuZZW #problem #programming: Hybridizing tabu search with mathematical programming for solving a single row layout problem (MY, XZ, XZ, CW), pp. 974–980.
ICST-2018-RyouR #automation #detection #fault #html #web: Automatic Detection of Visibility Faults by Layout Changes in HTML5 Web Pages (YR, SR), pp. 182–192.
CASE-2017-TanCT #automation #classification #evaluation #multi: Multiple binary classifiers to analyse decision of non-compliance: For automated evaluation of piping layout (WCT, IMC, HKT), pp. 80–85.
ICPR-2016-CorbelliBGC #analysis #classification #documentation: Historical document digitization through layout analysis and deep content classification (AC, LB, CG, RC), pp. 4077–4082.
KDD-2016-OmariKYS #web: Lossless Separation of Web Pages into Layout Code and Data (AO, BK, EY, SS), pp. 1805–1814.
MoDELS-2016-RueggLPKSH #automation #diagrams #incremental #migration: Incremental diagram layout for automated model migration (UR, RL, AP, AK, CDS, RvH), pp. 185–195.
ECOOP-2016-PoulsenNTV #memory management #semantics: Scopes Describe Frames: A Uniform Model for Memory Layout in Dynamic Semantics (CBP, PN, APT, EV), p. 26.
OOPSLA-2016-PanchekhaT #automation #reasoning #web: Automated reasoning for web page layout (PP, ET), pp. 181–194.
CASE-2016-TanCPT #automation #design #diagrams #evaluation #using: Automated design evaluation on layout of Piping and Instrumentation Diagram using Histogram of Connectivity (WCT, IMC, SJP, HKT), pp. 1295–1300.
CC-2016-MajetiMBS #architecture #automation #cpu #generative #gpu #kernel: Automatic data layout generation and kernel mapping for CPU+GPU architectures (DM, KSM, RB, VS), pp. 240–250.
DocEng-2015-EskenaziGO #documentation: The Delaunay Document Layout Descriptor (SE, PGK, JMO), pp. 167–175.
DocEng-2015-HassanH #automation #documentation #flexibility: Knuth-Plass Revisited: Flexible Line-Breaking for Automatic Document Layout (TH, AH), pp. 17–20.
DocEng-2015-KidoYTA #automation #documentation #optimisation: Document Layout Optimization with Automated Paraphrasing (YK, HY, GT, AA), pp. 13–16.
DocEng-2015-VernicaV #adaptation #framework #named #synthesis #web: AERO: An Extensible Framework for Adaptive Web Layout Synthesis (RV, NDV), pp. 187–190.
DRR-2015-ChenSWLHI #analysis #dataset #documentation: Ground truth model, tool, and dataset for layout analysis of historical documents (KC, MS, HW, ML, JH, RI), p. 940204.
SIGMOD-2015-FengLKX #in memory #memory management #named: ByteSlice: Pushing the Envelop of Main Memory Data Processing with a New Storage Layout (ZF, EL, BK, WX), pp. 31–46.
CHI-2015-ODonovanAH #design #interactive #named: DesignScape: Design with Interactive Layout Suggestions (PO, AA, AH), pp. 1221–1224.
HCI-UC-2015-JachK #online: Factors Influencing Online Shop Layout Preferences (KJ, MK), pp. 419–429.
MoDELS-2015-GregoricsGKDD #algorithm #diagrams #visualisation: Textual diagram layout language and visualization algorithm (BG, TG, GFK, AD, GD), pp. 196–205.
OOPSLA-2015-HottelierB #constraints #relational #synthesis: Synthesis of layout engines from relational constraints (TH, RB), pp. 74–88.
SAS-2015-ChoiCNS #javascript #named #type system: SJS: A Type System for JavaScript with Fixed Object Layout (WC, SC, GCN, KS), pp. 181–198.
ASE-2015-WalshMK #automation #detection #fault #web: Automatic Detection of Potential Layout Faults Following Changes to Responsive Web Pages (N) (TAW, PM, GMK), pp. 709–714.
DAC-2015-XiaoGWYTW #optimisation #self #verification: Layout optimization and template pattern verification for directed self-assembly (DSA) (ZX, DG, MDFW, HY, MCT, HSPW), p. 6.
ICST-2015-HalleBGB #constraints #testing #web: Testing Web Applications Through Layout Constraints (SH, NB, FG, GLB), pp. 1–8.
HCI-TMT-2014-SteigerLMKK: Deterministic Local Layouts through High-Dimensional Layout Stitching (MS, HLT, TM, AK, JK), pp. 643–651.
LCT-NLE-2014-PurgathoferL #architecture #harmful: Layout Considered Harmful: On the Influence of Information Architecture on Dialogue (PP, NL), pp. 216–225.
ICPR-2014-FernandezT #analysis #documentation: EM-Based Layout Analysis Method for Structured Documents (FCF, ORT), pp. 315–320.
MLDM-2014-BozkirS #named #similarity #visual notation #web: SimiLay: A Developing Web Page Layout Based Visual Similarity Search Engine (ASB, EAS), pp. 457–470.
SEKE-2014-ZhuangZL #fine-grained #framework #reuse #runtime: Runtime Code Reuse Attacks: A Dynamic Framework Bypassing Fine-Grained Address Space Layout Randomization (YZ, TZ, ZL), pp. 609–614.
SIGIR-2014-LinGHTXL #retrieval: A mathematics retrieval system for formulae in layout presentations (XL, LG, XH, ZT, YX, XL), pp. 697–706.
MoDELS-2014-Storrle #comprehension #diagrams #matter #on the #quality #uml: On the Impact of Layout Quality to Understanding UML Diagrams: Size Matters (HS), pp. 518–534.
OOPSLA-2014-UrecheBO #data transformation #representation: Late data layout: unifying data representation transformations (VU, EB, MO), pp. 397–416.
DAC-2014-DingCM #optimisation #throughput: Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout (YD, CC, WKM), p. 6.
DAC-2014-YuP #composition: Layout Decomposition for Quadruple Patterning Lithography and Beyond (BY, DZP), p. 6.
DocEng-2013-AlvaroZ: A shape-based layout descriptor for classifying spatial relationships in handwritten math (FA, RZ), pp. 123–126.
DocEng-2013-PiccoliO #automation #documentation #flexibility: Balancing font sizes for flexibility in automated document layout (RFBP, JBSdO), pp. 151–160.
DRR-2013-AzawiLB #documentation: WFST-based ground truth alignment for difficult historical documents with text modification and layout variations (MIAAA, ML, TMB).
ICDAR-2013-AntonacopoulosCPP #analysis #contest: ICDAR 2013 Competition on Historical Newspaper Layout Analysis (HNLA 2013) (AA, CC, CP, SP), pp. 1454–1458.
ICDAR-2013-WeiBSI #analysis #classification #documentation #evaluation: Evaluation of SVM, MLP and GMM Classifiers for Layout Analysis of Historical Documents (HW, MB, FS, RI), pp. 1220–1224.
GT-VMT-2013-MaierM #approach #diagrams: A Pattern-based Approach for Initial Diagram Layout (SM, MM).
HCI-UC-2013-BergmannMSO #automation #case study #generative #user study: Automatic Layout Generation for Digital Photo Albums: A User Study (FBB, IHM, MSS, JBSdO), pp. 117–126.
HIMI-D-2013-ChangSCH #design #interface #on the #performance #topic: On the Reading Performance of Text Layout, Switch Position, Topic of Text, and Luminance Contrast for Chinese E-books Interface Design (WTC, LHS, ZC, KCH), pp. 567–575.
SAC-2013-ChanHN #semantics #using #wiki #word: Computing semantic relatedness using word frequency and layout information of Wikipedia (PC, YH, SN), pp. 282–287.
CASE-2013-FerreiraR #comparison #design #performance #simulation #using: Performance comparison of the virtual cell layout with cellular and job shop configurations using simulation and design of experiments (JCEF, PAR), pp. 795–800.
DAC-2013-KuangY #approach #composition #performance: An efficient layout decomposition approach for triple patterning lithography (JK, EFYY), p. 6.
PDP-2013-FariaSS #data type #performance: Impact of Data Structure Layout on Performance (NF, RCS, JLS), pp. 116–120.
PPoPP-2013-LiuDJK #architecture #optimisation: Data layout optimization for GPGPU architectures (JL, WD, OJ, MTK), pp. 283–284.
DocEng-2012-AcebalBRL #css #implementation #javascript #named: ALMcss: a javascript implementation of the CSS template layout module (CFA, BB, MR, JMCL), pp. 23–32.
DocEng-2012-GangeMS: Optimal guillotine layout (GG, KM, PJS), pp. 13–22.
DocEng-2012-MoulderM #how #learning: Learning how to trade off aesthetic criteria in layout (PM, KM), pp. 33–36.
GT-VMT-2012-MaierM #ad hoc #automation #diagrams #editing: Layout Improvement in Diagram Editors by Automatic Ad-hoc Layout (SM, MM).
CHI-2012-TeoJB #named: CogTool-Explorer: a model of goal-directed user exploration that considers information layout (LT, BEJ, MHB), pp. 2479–2488.
SIGIR-2012-LeiCCIH #retrieval #scalability: Where is who: large-scale photo retrieval by facial attributes and canvas layout (YHL, YYC, BCC, LI, WHH), pp. 701–710.
ICSE-2012-Rodes #source code #stack #towards: Stack layout transformation: Towards diversity for securing binary programs (BR), pp. 1543–1546.
DAC-2012-FangCC #algorithm #composition #novel: A novel layout decomposition algorithm for triple patterning lithography (SYF, YWC, WYC), pp. 1185–1190.
DATE-2012-PonsMP #metric: Fixed origin corner square inspection layout regularity metric (MP, MNM, CP), pp. 1397–1402.
DocEng-2011-Brailsford #automation: Automated conversion of web-based marriage register data into a printed format with predefined layout (DFB), pp. 61–64.
DocEng-2011-GangeMMS #automation: Optimal automatic table layout (GG, KM, PM, PJS), pp. 23–32.
DocEng-2011-NebelingMSN #adaptation #effectiveness #web: Adaptive layout template for effective web content presentation in large-screen contexts (MN, FM, LS, MCN), pp. 219–228.
DocEng-2011-PiccoliCCOM #documentation #for free #interactive #novel: A novel physics-based interaction model for free document layout (RFBP, RC, NCC, JBSdO, IHM), pp. 153–162.
ICDAR-2011-AntonacopoulosCPP #analysis #contest #documentation: Historical Document Layout Analysis Competition (AA, CC, CP, SP), pp. 1516–1520.
ICDAR-2011-BaechlerI #analysis #multi #using: Multi Resolution Layout Analysis of Medieval Manuscripts Using Dynamic MLP (MB, RI), pp. 1185–1189.
ICDAR-2011-BukhariSB11a #analysis #documentation #image #performance: High Performance Layout Analysis of Arabic and Urdu Document Images (SSB, FS, TMB), pp. 1275–1279.
ICDAR-2011-ClausnerPA #documentation #named: Aletheia — An Advanced Document Layout and Text Ground-Truthing System for Production Environments (CC, SP, AA), pp. 48–52.
ICDAR-2011-ClausnerPA11a #analysis #documentation #evaluation #performance: Scenario Driven In-depth Performance Evaluation of Document Layout Analysis Methods (CC, SP, AA), pp. 1404–1408.
ICDAR-2011-DiemKS #analysis #classification #documentation: Text Classification and Document Layout Analysis of Paper Fragments (MD, FK, RS), pp. 854–858.
ICDAR-2011-GarzSD #analysis #using: Layout Analysis for Historical Manuscripts Using Sift Features (AG, RS, MD), pp. 508–512.
ICDAR-2011-HadjarI #generative: Minimizing User Annotations in the Generation of Layout Ground-Truthed Data (KH, RI), pp. 703–707.
JCDL-2011-SandersonASS #collaboration #named: SharedCanvas: a collaborative model for medieval manuscript layout dissemination (RS, BA, RS, HVdS), pp. 175–184.
AGTIVE-2011-MaierM #diagrams #editing #integration: Integration of a Pattern-Based Layout Engine into Diagram Editors (SM, MM), pp. 89–96.
CHI-2011-FrischKLD #multi #tool support: Grids & guides: multi-touch layout and alignment tools (MF, SK, RL, RD), pp. 1615–1618.
CHI-2011-NebelingMN #evaluation #metric: Metrics for the evaluation of news site content layout in large-screen contexts (MN, FM, MCN), pp. 1511–1520.
DUXU-v2-2011-NakataniOKNH #case study #internet: The Layout for the User-Friendly Manual: Case Study on an Internet Set-Up Manual (MN, TO, YK, AN, SH), pp. 40–45.
POPL-2011-RamananandroRL #c++ #inheritance #multi #verification: Formal verification of object layout for c++ multiple inheritance (TR, GDR, XL), pp. 67–80.
SLE-2011-JongeV #algorithm #refactoring: An Algorithm for Layout Preservation in Refactoring Transformations (MdJ, EV), pp. 40–59.
CC-2011-HenrettySPFRS #architecture: Data Layout Transformation for Stencil Computations on Short-Vector SIMD Architectures (TH, KS, LNP, FF, JR, PS), pp. 225–245.
DAC-2011-BanLP #2d #composition #flexibility #framework: Flexible 2D layout decomposition framework for spacer-type double pattering lithography (YB, KL, DZP), pp. 789–794.
DAC-2011-BanY #modelling #optimisation: Layout aware line-edge roughness modeling and poly optimization for leakage minimization (YB, JSY), pp. 447–452.
DAC-2011-HsuSPCH #algorithm #distributed #geometry: A distributed algorithm for layout geometry operations (KTH, SS, YCP, CC, TYH), pp. 182–187.
DAC-2011-NandakumarM #3d: Layout effects in fine grain 3D integrated regular microprocessor blocks (VSN, MMS), pp. 639–644.
DAC-2011-RyzhenkoB #geometry #physics #synthesis: Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries (NR, SB), pp. 83–88.
DATE-2011-GraupnerJW #approach #design #generative #optimisation: Generator based approach for analog circuit and layout design and optimization (AG, RJ, RW), pp. 1675–1680.
HPDC-2011-SongYCS #file system #parallel: A cost-intelligent application-specific data layout scheme for parallel file systems (HS, YY, YC, XHS), pp. 37–48.
DocEng-2010-BaechlerI: Medieval manuscript layout model (MB, RI), pp. 275–278.
DocEng-2010-BilaucaH #automation: A new model for automated table layout (MB, PH), pp. 169–176.
DocEng-2010-BilaucaH10a #authoring #documentation #performance #tool support: Table layout performance of document authoring tools (MB, PH), pp. 199–202.
DocEng-2010-Lumley #documentation #functional #invariant: Pre-evaluation of invariant layout in functional variable-data documents (JWL), pp. 251–254.
DocEng-2010-SpenglerG #documentation #random #web: Document structure meets page layout: loopy random fields for web news content extraction (AS, PG), pp. 151–160.
DocEng-2010-TerradesTSRVJ #analysis #documentation #interactive: Interactive layout analysis and transcription systems for historic handwritten documents (ORT, AHT, NS, VR, EV, AJ), pp. 219–222.
SIGMOD-2010-OzmenSSD #database: Workload-aware storage layout for database systems (OO, KS, JS, SD), pp. 939–950.
CSEET-2010-SharifM #design pattern #detection: The Effects of Layout on Detecting the Role of Design Patterns (BS, JIM), pp. 41–48.
ICSM-2010-SharifM #comprehension #design pattern #eye tracking: An eye tracking study on the effects of layout in understanding the role of design patterns (BS, JIM), pp. 1–10.
AIIDE-2010-TutenelSBK #problem #semantics: A Semantic Scene Description Language for Procedural Layout Solving Problems (TT, RMS, RB, KJdK).
SOFTVIS-2010-AlbrechtEHK #algorithm #automation #process: An automatic layout algorithm for BPEL processes (BA, PE, MH, MK), pp. 173–182.
SOFTVIS-2010-Zeckzer #matrix #using #visualisation: Visualizing software entities using a matrix layout (DZ), pp. 207–208.
SAC-2010-LecerfC #documentation #ranking #retrieval #scalability: Scalable indexing for layout based document retrieval and ranking (LL, BC), pp. 28–32.
SAC-2010-RiponGHT #approach #multi #problem #using: Multi-objective evolutionary approach for solving facility layout problem using local search (KSNR, KG, MH, JT), pp. 1155–1156.
SAC-2010-RyuCC #image #named #using: PHOTOLAND: a new image layout system using spatio-temporal information in digital photos (DSR, WKC, HGC), pp. 1884–1891.
CASE-2010-WangKF #approach #assembly #hybrid: A hybrid approach for dynamic assembly shop floor layout (LW, SK, HYF), pp. 604–609.
CGO-2010-WangWY #memory management #on the: On improving heap memory layout by dynamic pool allocation (ZW, CW, PCY), pp. 92–100.
DAC-2010-BanP #modelling #optimisation #robust: Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography (YB, DZP), pp. 408–411.
DAC-2010-YangALLP #3d #analysis #optimisation: TSV stress aware timing analysis with applications to 3D-IC layout optimization (JSY, KA, YJL, SKL, DZP), pp. 803–806.
DocEng-2009-BalinskyHW: Aesthetically-driven layout engine (HB, JRH, AW), pp. 119–122.
HT-2009-Francisco-RevillaC #web: Interpreting the layout of web pages (LFR, JC), pp. 157–166.
ICDAR-2009-AntonacopoulosBPP #analysis #dataset #documentation #evaluation #performance: A Realistic Dataset for Performance Evaluation of Document Layout Analysis (AA, DB, CP, SP), pp. 296–300.
ICDAR-2009-FerilliBEB #analysis: A Distance-Based Technique for Non-Manhattan Layout Analysis (SF, MB, FE, TMAB), pp. 231–235.
ICDAR-2009-GordoV #classification #documentation #invariant #retrieval: A Rotation Invariant Page Layout Descriptor for Document Classification and Retrieval (AG, EV), pp. 481–485.
ICDAR-2009-MalleronEEDR #analysis #documentation: Text Lines and Snippets Extraction for 19th Century Handwriting Documents Layout Analysis (VM, VE, HE, SDC, PR), pp. 1001–1005.
ICDAR-2009-MontreuilGHN #2d #documentation #random #using: Unconstrained Handwritten Document Layout Extraction Using 2D Conditional Random Fields (FM, EG, LH, SN), pp. 853–857.
ICDAR-2009-Smith #analysis #detection #hybrid: Hybrid Page Layout Analysis via Tab-Stop Detection (RWS), pp. 241–245.
ICDAR-2009-TatsumiHK #optimisation: Context-oriented Layout Optimization of Large-Print Textbooks (IT, HH, MK), pp. 1016–1020.
VISSOFT-2009-SharifM #comprehension #diagrams #empirical #uml: The effect of layout on the comprehension of UML class diagrams: A controlled experiment (BS, JIM), pp. 11–18.
ICEIS-HCI-2009-TroianoBAC #algorithm #mobile #optimisation #search-based #web: Web Form Page in Mobile Devices — Optimization of Layout with a Simple Genetic Algorithm (LT, CB, RA, GC), pp. 118–123.
DAC-2009-YeLCC #analysis #process #variability: Variability analysis under layout pattern-dependent rapid-thermal annealing process (YY, FL, MC, YC), pp. 551–556.
DATE-2009-GrabBCCFLS #synthesis: Analog layout synthesis — Recent advances in topological approaches (HG, FB, RCL, YWC, FVF, MPHL, MS), pp. 274–279.
DocEng-2008-HurstM: Satisficing scrolls: a shortcut to satisfactory layout (NH, KM), pp. 131–140.
DocEng-2008-IorioFVLW #abstraction: Higher-level layout through topological abstraction (ADI, LF, FV, JWL, TW), pp. 90–99.
DocEng-2008-Oliveira #algorithm #automation #documentation: Two algorithms for automatic document page layout (JBSdO), pp. 141–149.
WCRE-2008-KuhnLN #consistency: Consistent Layout for Thematic Software Maps (AK, PL, ON), pp. 209–218.
GT-VMT-2008-MaierM #algorithm: A Static Layout Algorithm for DiaMeta (SM, MM).
CHI-2008-GoldbergHM #distance: Information distance and orientation in liquid layout (JHG, JH, LM), pp. 1153–1156.
SOFTVIS-2008-Eichelberger #automation #case study #diagrams #uml: Automatic layout of UML use case diagrams (HE), pp. 105–114.
ICPR-2008-BridsonA #analysis #approach #evaluation #geometry #performance: A geometric approach for accurate and efficient performance evaluation of layout analysis methods (DB, AA), pp. 1–4.
ICPR-2008-FerilliBBE #comprehension #documentation #incremental #machine learning: Incremental machine learning techniques for document layout understanding (SF, MB, TMAB, FE), pp. 1–4.
ICPR-2008-JhaN #independence #representation: Wang Notation Tool: Layout independent representation of tables (PJ, GN), pp. 1–4.
ICPR-2008-ShafaitBKB #analysis #modelling #statistics #variability: Background variability modeling for statistical layout analysis (FS, JvB, DK, TMB), pp. 1–4.
ECOOP-2008-ZhangH #adaptation #online: Online Phase-Adaptive Data Layout Selection (CZ, MH), pp. 309–334.
ASE-2008-MooreS #analysis #design: Combining the Analysis of Spatial Layout and Text to Support Design Exploration (JMM, FMSI), pp. 379–382.
SAC-2008-ChidlovskiiL #dependence #documentation #network: Stacked dependency networks for layout document structuring (BC, LL), pp. 424–428.
SAC-2008-TakasuA #analysis #documentation #information management #probability: Information extraction from scanned documents by stochastic page layout analysis (AT, KA), pp. 447–448.
CASE-2008-TeoP #heuristic #hybrid #problem: A hybrid ACO/PSO heuristic to solve single row layout problem (YTT, SGP), pp. 597–602.
DAC-2008-TamPB #analysis #automation #locality #precise #using: Precise failure localization using automated layout analysis of diagnosis candidates (WCT, OP, RD(B), pp. 367–372.
DATE-2008-ChakrabortySP #optimisation: Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices (AC, SXS, DZP), pp. 849–855.
LCTES-2008-ChoPIDPK #array #compilation #data access #optimisation: Compiler driven data layout optimization for regular/irregular array access patterns (DC, SP, II, ND, YP, SK), pp. 41–50.
PPoPP-2008-NishtalaAC #communication #performance: Performance without pain = productivity: data layout and collective communication in UPC (RN, GA, CC), pp. 99–110.
DRR-2007-ZouLT #analysis #online: Online medical journal article layout analysis (JZ, DXL, GRT).
ICDAR-2007-AntonacopoulosB #analysis #framework #performance: Performance Analysis Framework for Layout Analysis Methods (AA, DB), pp. 1258–1262.
ICDAR-2007-BulacuKSZ #analysis #documentation: Layout Analysis of Handwritten Historical Documents for Searching the Archive of the Cabinet of the Dutch Queen (MB, RvK, LS, TvdZ), pp. 357–361.
ICDAR-2007-Burget #documentation #html #information management: Layout Based Information Extraction from HTML Documents (RB), pp. 624–628.
ICDAR-2007-ChenMT #documentation #logic #recognition: Simultaneous Layout Style and Logical Entity Recognition in a Heterogeneous Collection of Documents (SC, SM, GT), pp. 118–122.
ICDAR-2007-HiranoOOY #analysis #documentation #information management: Text and Layout Information Extraction from Document Files of Various Formats Based on the Analysis of Page Description Language (TH, YO, YO, FY), pp. 262–266.
ICDAR-2007-LemaitreGP #2d #analysis #approach #markov: Preliminary experiments in layout analysis of handwritten letters based on textural and spatial information and a 2D Markovian approach (ML, EG, FJP), pp. 1023–1027.
ICDAR-2007-MinagawaFTF #analysis #image #logic: Logical Structure Analysis for Form Images with Arbitrary Layout by Belief Propagation (AM, YF, HT, KF), pp. 714–718.
AGTIVE-2007-MaierM #algorithm #editing #metamodelling #modelling: A Generic Layout Algorithm for Meta-model Based Editors (SM, MM), pp. 66–81.
HCI-IPT-2007-ChenLWS: Screen Layout on Color Search Task for Customized Product Color Combination Selection (CYC, YJL, FGW, CFS), pp. 32–40.
SIGIR-2007-ChibaneD #algorithm #segmentation #topic #visual notation #web: A web page topic segmentation algorithm based on visual criteria and content layout (IC, BLD), pp. 817–818.
SIGIR-2007-Obrador #documentation #image #retrieval: Document layout and color driven image retrieval (PO), pp. 889–890.
CASE-2007-FogelBRSMG #automation #modelling #symmetry: Automated Tracking of Pallets in Warehouses: Beacon Layout and Asymmetric Ultrasound Observation Models (MF, NB, HR, JS, MQM, KG), pp. 678–685.
CC-2007-JeonSH #data access #using: Layout Transformations for Heap Objects Using Static Access Patterns (JJ, KS, HH), pp. 187–201.
CGO-2007-RamanHM #optimisation #parallel #source code #thread: Structure Layout Optimization for Multithreaded Programs (ER, RH, SM), pp. 271–282.
DAC-2007-TsaiZT #design #modelling: Modeling Litho-Constrained Design Layout (MCT, DZ, ZT), pp. 354–357.
DocEng-2006-HurstMA #problem: Solving the simple continuous table layout problem (NH, KM, DWA), pp. 28–30.
DocEng-2006-LumleyGR: Resolving layout interdependency with presentational variables (JWL, RG, OR), pp. 95–97.
DocEng-2006-MacdonaldBL #documentation: Evaluating invariances in document layout functions (AJM, DFB, JWL), pp. 25–27.
DRR-2006-LinCND #comprehension #documentation #version control: Active document versioning: from layout understanding to adjustment (XL, HC, GN, ED).
JCDL-2006-ZouLT #analysis #geometry #online #segmentation: Combining DOM tree and geometric layout analysis for online medical journal article segmentation (JZ, DXL, GRT), pp. 119–128.
SOFTVIS-2006-GauvinB #automation #data flow #programming language #visual notation: Transparency, holophrasting, and automatic layout applied to control structures for visual dataflow programming languages (SG, OB), pp. 67–75.
SOFTVIS-2006-GudenbergNEE #diagrams #uml: Evolutionary layout of UML class diagrams (JWvG, AN, ME, HE), pp. 163–164.
SOFTVIS-2006-Jucknath-JohnGT #development #modelling: Evolutionary layout: preserving the mental map during the development of class models (SJJ, DG, GT), pp. 165–166.
ECIR-2006-YaoWLLM #ranking #visual notation #web: Ranking Web News Via Homepage Visual Layout and Cross-Site Voting (JY, JW, ZL, ML, WYM), pp. 131–142.
ICPR-v2-2006-LiuCC #analysis #image: Latent Layout Analysis for Discovering Objects in Images (DL, DC, TC), pp. 468–471.
ICPR-v4-2006-TokaiH #multi #navigation: Attention Navigation by Keeping Screen Layout for Switching Multiple Views (ST, HH), pp. 766–769.
PPDP-2006-NguyenO #compilation #ml #morphism #polymorphism: Compiling ML polymorphism with explicit layout bitmap (HDN, AO), pp. 237–248.
CGO-2006-HundtMC #optimisation: Practical Structure Layout Optimization and Advice (RH, SM, DRC), pp. 233–244.
DATE-2006-AngioliniMCBR: Contrasting a NoC and a traditional interconnect fabric with layout awareness (FA, PM, SC, LB, LR), pp. 124–129.
DATE-2006-IizukaIA #optimisation: Timing-driven cell layout de-compaction for yield optimization by critical area minimization (TI, MI, KA), pp. 884–889.
DATE-2006-KastnerGHBKBS #communication #optimisation #synthesis: Layout driven data communication optimization for high level synthesis (RK, WG, XH, FB, AK, PB, MS), pp. 1185–1190.
LCTES-2006-PlatenE #feedback #optimisation: Feedback linking: optimizing object code layout for updates (CvP, JE), pp. 2–11.
PDP-2006-Sobe #adaptation #distributed: Adaptations of Block Layout in Distributed Storage Systems (PS), pp. 163–172.
DocEng-2005-LumleyGR #documentation #framework: A framework for structure, layout & function in documents (JWL, RG, OR), pp. 32–41.
ICDAR-2005-BerardiACM #analysis #process: A color-based layout analysis to process censorship cards of film archives (MB, OA, MC, DM), pp. 1110–1114.
ICDAR-2005-ChaoL #documentation #reuse: Capturing the Layout of Electronic Documents for Reuse in Variable Data Printing (HC, XL), pp. 940–944.
ICDAR-2005-HuangDDGH #documentation #ranking: Document Ranking by Layout Relevance (MH, DD, DSD, LG, BAH), pp. 362–366.
ICDAR-2005-Lin #documentation #synthesis: Active Document Layout Synthesis (XL), pp. 86–90.
ICDAR-2005-MarinaiMS #documentation #image #reduction #retrieval: Layout based document image retrieval by means of XY tree reduction (SM, EM, GS), pp. 432–436.
ICDAR-2005-Sun #documentation #segmentation: Page Segmentation for Manhattan and Non-Manhattan Layout Documents via Selective CRLA (HMS), pp. 116–120.
ICDAR-2005-TakiguchiOM #comprehension #recognition #semantics: A Fundamental Study of Output Translation from Layout Recognition and Semantic Understanding System for Mathematical Formulae (YT, MO, YM), pp. 745–749.
ICDAR-2005-YingsaereeK #analysis #detection #documentation #rule-based: Rule-based Middle-level Character Detection for Simplifying Thai Document Layout Analysis (CY, AK), pp. 888–892.
IWPC-2005-SunW #comprehension #diagrams #on the #uml: On Evaluating the Layout of UML Class Diagrams for Program Comprehension (DS, KW), pp. 317–326.
SOFTVIS-2005-NoackL #graph #modelling: A space of layout styles for hierarchical graph models of software systems (AN, CL), pp. 155–164.
VISSOFT-2005-AndriyevskaDSM #architecture #diagrams #uml: Evaluating UML Class Diagram Layout based on Architectural Importance (OA, ND, BS, JIM), pp. 14–19.
PLDI-2005-LattnerA #automation #data type #performance: Automatic pool allocation: improving performance by controlling data structure layout in the heap (CL, VSA), pp. 129–142.
SAC-2005-Hosobe #constraints #documentation #linear #web: Solving linear and one-way constraints for web document layout (HH), pp. 1252–1253.
CASE-2005-ZhuD #design #synthesis: Grasp synthesis and fixture layout design in discrete domain (XZ, HD), pp. 73–78.
DAC-2005-NieKT #incremental: A watermarking system for IP protection by a post layout incremental router (TN, TK, MT), pp. 218–221.
DATE-2005-ChenKK #approach #constraints #memory management #network #optimisation: A Constraint Network Based Approach to Memory Layout Optimization (GC, MTK, MK), pp. 1156–1161.
DATE-2005-ChenLL #integration #multi #verification: Integration, Verification and Layout of a Complex Multimedia SOC (CLC, JYL, YLL), pp. 1116–1117.
PPoPP-2005-SonCKC #compilation #energy #parallel: Exposing disk layout to compiler for reducing energy consumption of parallel disk based systems (SWS, GC, MTK, ANC), pp. 174–185.
DocEng-2004-HarringtonNJRT #automation #documentation #metric: Aesthetic measures for automated document layout (SJH, JFN, RPJ, PGR, NT), pp. 109–111.
VLDB-2004-ShaoSSAG #memory management #named: Clotho: Decoupling memory page layout from storage organization (MS, JS, SWS, AA, GRG), pp. 696–707.
CGO-2004-SoHZ #memory management #parallel: Custom Data Layout for Memory Parallelism (BS, MWH, HEZ), pp. 291–302.
DAC-2004-AlpertHHQ #flexibility #performance #physics: Fast and flexible buffer trees that navigate the physical layout environment (CJA, MH, JH, STQ), pp. 24–29.
DAC-2004-JerkeLS #design: Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs (GJ, JL, JS), pp. 181–184.
DAC-2004-XuPB #named #optimisation: ORACLE: optimization with recourse of analog circuits including layout extraction (YX, LTP, SPB), pp. 151–154.
DATE-v1-2004-ThepayasuwanD #architecture #synthesis: Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip (NT, AD), pp. 108–113.
DATE-v2-2004-VrankenSW: Impact of Test Point Insertion on Silicon Area and Timing during Layout (HPEV, FSS, HJW), pp. 810–815.
ICDAR-2003-Breuel #algorithm #analysis #documentation: An Algorithm for Finding Maximal Whitespace Rectangles at Arbitrary Orientations for Document Layout Analysis (TMB), pp. 66–70.
ICDAR-2003-EglinB #classification #documentation #query #similarity #visual notation: Document page similarity based on layout visual saliency: Application to query by example and document classification (VE, SB), pp. 1208–1212.
ICDAR-2003-FutrelleSCG #analysis #classification #diagrams #documentation: Extraction, layout analysis and classification of diagrams in PDF documents (RPF, MS, CC, AEG), pp. 1007–1014.
ICDAR-2003-MalerbaEACB #approach #documentation #machine learning: Correcting the Document Layout: A Machine Learning Approach (DM, FE, OA, MC, MB), p. 97–?.
SIGMOD-2003-PadmanabhanBMCH #clustering #multi: Multi-Dimensional Clustering: A New Data Layout Scheme in DB2 (SP, BB, TM, LC, MH), pp. 637–641.
SOFTVIS-2003-EiglspergerKS #approach #automation #diagrams #uml: A Topology-Shape-Metrics Approach for the Automatic Layout of UML Class Diagram (ME, MK, MS), pp. 189–198.
VISSOFT-2003-EichelbergerG #diagrams #state of the art #uml: UML Class Diagrams – State of the Art in Layout Techniques (HE, JWvG), pp. 30–34.
VISSOFT-2003-EichelbergerW #diagrams #uml: Demonstration of Advanced Layout of UML Class Diagrams by SugiBib (HE, JW), pp. 58–59.
ICML-2003-BerardiCEM #analysis #learning #logic programming #source code: Learning Logic Programs for Layout Analysis Correction (MB, MC, FE, DM), pp. 27–34.
ECOOP-2003-ZibinG #2d: Two-Dimensional Bi-directional Object Layout (YZ, JYG), pp. 329–350.
POPL-2003-PetersenHCP #memory management #type system: A type theory for memory allocation and data layout (LP, RH, KC, FP), pp. 172–184.
ICSE-2003-SeyboldGMM #adaptation #effectiveness #modelling #visual notation: An Effective Layout Adaptation Technique for a Graphical Modeling Tool (CS, MG, SM, NMS), pp. 826–827.
DAC-2003-ChenCCKMSYZ #algebra #clustering #multi: An algebraic multigrid solver for analytical placement with layout based clustering (HC, CKC, NCC, ABK, JFM, PS, BY, ZZ), pp. 794–799.
DAC-2003-ChoiK #design #embedded #memory management #performance: Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design (YC, TK), pp. 881–886.
DATE-2003-GirardiB #automation #generative #named: LIT — An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks (AG, SB), pp. 11106–11107.
DATE-2003-HettiaratchiC #approach #clustering #energy #performance: Mesh Partitioning Approach to Energy Efficient Data Layout (SH, PYKC), pp. 11076–11081.
DATE-2003-RenczSP #algorithm #performance #simulation: A Fast Algorithm for the Layout Based Electro-Thermal Simulation (MR, VS, AP), pp. 11032–11037.
CIKM-2002-RosenfeldFA #documentation #visual notation: Structural extraction from visual layout of documents (BR, RF, YA), pp. 203–210.
ICPR-v3-2002-LuT #analysis #documentation #image #word: Word Spotting in Chinese Document Images without Layout Analysis (YL, CLT), pp. 57–60.
SAC-2002-KangY #multi: Smoothed fetching: bridging the data layout and transmission schemes in multimedia servers (SK, HYY), pp. 755–760.
DATE-2002-KutzschebauchS #composition: Layout Driven Decomposition with Congestion Consideration (TK, LS), pp. 672–676.
DATE-2002-SommerRHGMMECSN #design #specification #top-down: From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications (RS, IRH, EH, UG, PM, FM, KE, CC, PS, GN), pp. 884–891.
PDP-2002-SeinstraK #memory management #message passing #modelling #source code: Incorporating Memory Layout in the Modeling of Message Passing Programs (FJS, DK), pp. 293–300.
ICDAR-2001-HaseYSS #recognition: Alignment of Free Layout Color Texts for Character Recognition (HH, MY, TS, CYS), pp. 932–936.
ICDAR-2001-Hurst #using: Layout and Language: Exploring Text Block Discovery in Tables Using Linguistic Resources (MH), pp. 523–527.
ICDAR-2001-LiuLHY #algorithm #analysis #component: A New Component Based Algorithm for Newspaper Layout Analysis (FL, YL, DH, MY), pp. 1176–1180.
ICDAR-2001-WongSA01a #analysis #using: Use of Colour in Form Layout Analysis (WSW, NS, TA), pp. 942–946.
DAC-2001-BeniniMMMP #architecture #embedded #memory management #synthesis: From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip (LB, LM, AM, EM, MP), pp. 784–789.
DAC-2001-RiegerMP #design: Layout Design Methodologies for Sub-Wavelength Manufacturing (MLR, JPM, SP), pp. 85–88.
DAC-2001-SchellenbergTCS #design: Adoption of OPC and the Impact on Design and Layout (FMS, OT, LC, BS), pp. 89–92.
DAC-2001-SolomonH #using: Using Texture Mapping with Mipmapping to Render a VLSI Layout (JS, MH), pp. 500–505.
DATE-2001-KoranneG #analysis #automation #geometry #on the: On automatic analysis of geometrically proximate nets in VSLI layout (SK, OPG), p. 818.
DATE-2001-KulkarniGMCM #embedded #multi: Cache conscious data layout organization for embedded multimedia applications (CK, CG, MM, FC, HDM), pp. 686–693.
DATE-2001-MacchiaruloBM #generative #on the fly: On-the-fly layout generation for PTL macrocells (LM, LB, EM), pp. 546–551.
IFL-2000-Grelck #array #effectiveness: Improving Cache Effectiveness through Array Data Layout Manipulation in SAC (CG), pp. 231–248.
ICPR-v1-2000-Mitchell #analysis #documentation #segmentation #using: Document Page Segmentation and Layout Analysis Using Soft Ordering (PEM, HY), pp. 1458–1461.
ICPR-v4-2000-OkunP #analysis #automation #documentation #evaluation #generative: Automatic Ground-Truth Generation for Skew-Tolerance Evaluation of Document Layout Analysis Methods (OO, MP), pp. 4376–4379.
ICPR-v4-2000-RyuLK #analysis #documentation #geometry #independence: Parameter-Independent Geometric Document Layout Analysis (DSR, SWL, SMK), pp. 4397–4400.
ICPR-v4-2000-WatanabeS #analysis #documentation: Layout Analysis of Complex Documents (TW, TS), pp. 4447–4450.
DAC-2000-RanterMPVSGS #automation #design #named: CYCLONE: automated design and layout of RF LC-oscillators (CDR, BDM, GVdP, PJV, MS, GGEG, WMCS), pp. 11–14.
DATE-2000-BouraiS #optimisation: Layout Compaction for Yield Optimization via Critical Area Minimization (YB, CJRS), pp. 122–125.
HPCA-2000-BurnsG #question #smt: Quantifying the SMT Layout Overhead — Does SMT Pull Its Weight? (JB, JLG), pp. 109–120.
ICDAR-1999-Hobby #classification #composition #geometry: Page Decomposition and Signature Finding via Shape Classification and Geometric Layout (JDH), pp. 555–558.
ICDAR-1999-HuKW #classification #comparison #documentation #image: Document Image Layout Comparison and Classification (JH, RSK, GTW), pp. 285–288.
HCI-CCAD-1999-Stempfhuber #user interface #visual notation: Dynamic spatial layout in graphical user interfaces (MS), pp. 137–141.
OOPSLA-1999-SweeneyG #inheritance #memory management #multi: Space and Time-Efficient Memory Layout for Multiple Inheritance (PFS, JYG), pp. 256–275.
PLDI-1999-ChilimbiHL: Cache-Conscious Structure Layout (TMC, MDH, JRL), pp. 1–12.
ICSE-1999-HolderBG #distributed: Dynamic Layout of Distributed Applications in FarGo (OH, IBS, HG), pp. 163–173.
DAC-1999-BalasaL #representation #using: Module Placement for Analog Layout Using the Sequence-Pair Representation (FB, KL), pp. 274–279.
DAC-1999-KhatriMBOS #novel: A Novel VLSI Layout Fabric for Deep Sub-Micron Applications (SPK, AM, RKB, RHJMO, ALSV), pp. 491–496.
DAC-1999-MukherjeeSML #novel #synthesis: Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique (AM, RS, MMS, SIL), pp. 466–471.
DAC-1999-YehKSW #design #using: Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs (CWY, YSK, SJS, JSW), pp. 62–67.
HPCA-1999-SchwarzSB #development #permutation: Permutation Development Data Layout (PDDL) (TJES, JS, WAB), pp. 214–217.
ICPR-1998-TingL #linear: Linear layout processing (AT, MKHL), pp. 403–405.
DAC-1998-KrauterM #analysis: Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis (BK, SM), pp. 303–308.
DAC-1998-LiK #verification: Layout Extraction and Verification Methodology CMOS I/O Circuits (TL, SMK), pp. 291–296.
DAC-1998-MassoudMBW: Layout Techniques for Minimizing On-Chip Interconnect Self Inductance (YM, SSM, TB, JW), pp. 566–571.
DATE-1998-ArsintescuO #constraints: Constraints Space Management for the Layout of Analog IC’s (BGA, RHJMO), pp. 971–972.
DATE-1998-PrietoRGPHR #approach #design #fault #predict #testing: An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits (JAP, AR, IAG, EJP, JLH, AMDR), pp. 905–909.
ICDAR-1997-HurstD: Layout and Language: Preliminary Investigations in Recognizing the Structure of Tables (MH, SD), pp. 1043–1047.
ICDAR-1997-Ishitani #analysis #documentation: Document Layout Analysis Based on Emergent Computation (YI), pp. 45–50.
ICDAR-1997-WatanabeH #automation #comprehension: Automatic Acquisition of Layout Knowledge for Understanding Business Cards (TW, XH), pp. 216–220.
ICALP-1997-EilamFZ #network #problem: A Complete Characterization of the Path Layout Construction Problem for ATM Networks with Given Hop Count and Load (TE, MF, SZ), pp. 527–537.
RE-1997-DarimontDML #analysis #integration #named #requirements: GRAIL/KAOS: An Environment for Goal-Driven Requirements Analysis, Integration and Layout (RD, ED, PM, AvL), p. 140.
DAC-1997-GuptaH #2d #generative #named #optimisation: CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells (AG, JPH), pp. 452–455.
DAC-1997-GuruswamyMDRCFJ #automation #library #named #standard #synthesis: CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries (MG, RLM, DD, SR, VC, AF, LGJ), pp. 327–332.
DAC-1997-KimK #algorithm #design #performance: An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design (JK, SMK), pp. 456–459.
DAC-1997-Lakos: Technology Retargeting for IC Layout (JL), pp. 460–465.
DAC-1997-MurofushiIMM #power management: Layout Driven Re-synthesis for Low Power Consumption LSIs (MM, TI, MM, TM), pp. 666–669.
EDTC-1997-SeongK #clustering #design: Two-way partitioning based on direction vector [layout design] (KSS, CMK), pp. 306–310.
EDTC-1997-WalczowskiNWS #generative #web: Analogue layout generation by World Wide Web server-based agents (LTW, DN, WAJW, KHS), pp. 384–388.
ICPR-1996-NakajimaTKY #analysis #process #verification: Analysis of address layout on Japanese handwritten mail-a hierarchical process of hypothesis verification (NN, TT, TK, KY), pp. 726–731.
SEKE-1996-OrjiN #interactive #on-demand: Data Layout for Interactive Video-on-Demand Storage Systems (CUO, KCN), pp. 285–292.
DAC-1996-ChenLH: Layout Driven Selecting and Chaining of Partial Scan (CSC, KHL, TH), pp. 262–267.
DAC-1996-WunderLM #concept #modelling #named #simulation: VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems (BW, GL, KDMG), pp. 119–124.
STOC-1996-AggarwalKW #trade-off: Node-Disjoint Paths on the Mesh and a New Trade-Off in VLSI Layout (AA, JMK, DPW), pp. 585–594.
ICDAR-v1-1995-EspositoMS #analysis #approach #knowledge-based: A knowledge-based approach to the layout analysis (FE, DM, GS), pp. 466–471.
ICDAR-v1-1995-LefevreR #documentation #named: ODIL: an SGML description language of the layout structure of documents (PL, FR), pp. 480–488.
ICDAR-v2-1995-AzoklyI #documentation #segmentation: A language for document generic layout description and its use for segmentation into regions (AA, RI), pp. 1123–1126.
ICDAR-v2-1995-Liu-GongDP #analysis #documentation #recognition: A general analysis system for document’s layout structure recognition (YHLG, BD, HNP), pp. 597–600.
OOPSLA-1995-Myers #bidirectional #compilation: Bidirectional Object Layout for Separate Compilation (ACM), pp. 124–139.
PLDI-1995-ColemanM #using: Tile Size Selection Using Cache Organization and Data Layout (SC, KSM), pp. 279–290.
DAC-1995-GeloshS #modelling #performance #tool support: Deriving Efficient Area and Delay Estimates by Modeling Layout Tools (DSG, DES), pp. 402–407.
DAC-1995-HagenHK #heuristic #quantifier: Quantified Suboptimality of VLSI Layout Heuristics (LWH, DJHH, ABK), pp. 216–221.
DAC-1995-RekhiTL #automation #synthesis: Automatic Layout Synthesis of Leaf Cells (SR, JDT, DHL), pp. 267–272.
DAC-1994-ChangCWM #logic #synthesis: Layout Driven Logic Synthesis for FPGAs (SCC, KTC, NSW, MMS), pp. 308–313.
EDAC-1994-AhmadM #automation #named #reasoning: AREAL: Automated Reasoning Expert for Analogue Layout (HHA, RJM), p. 659.
ICDAR-1993-Conway #approach #documentation #parsing #recognition: Page grammars and page parsing. A syntactic approach to document layout recognition (AC), pp. 761–764.
ICDAR-1993-HaoWN #analysis #approach #classification #documentation #segmentation: Nested segmentation: an approach for layout analysis in document classification (XH, JTLW, PAN), pp. 319–322.
ICDAR-1993-HerrmannS #documentation #image #retrieval #using: Retrieval of document images using layout knowledge (PH, GS), pp. 537–540.
ICDAR-1993-IttnerB #analysis: Language-free layout analysis (DJI, HSB), pp. 336–340.
ICDAR-1993-IwaneYI #analysis #approach #classification #documentation #functional #image: A functional classification approach to layout analysis of document images (KI, MY, OI), pp. 778–781.
ICDAR-1993-KiseYBF #documentation #incremental: Incremental acquisition of knowledge about layout structures from examples of documents (KK, NY, NB, KF), pp. 668–671.
ICDAR-1993-WieserP #analysis #image: Layout and analysis: Finding text, titles, and photos in digital images of newspaper pages (JW, AP), pp. 774–777.
HCI-SHI-1993-Graf #constraints #multi #named: LAYLAB — A Constraint-Based Layout Manager for Multimedia Presentations (WG), pp. 446–451.
HCI-SHI-1993-HerrmannK: Supporting Instead of Replacing the Planner — An Intelligent Assistant System for Factory Layout Planning (JH, MK), pp. 796–801.
HCI-SHI-1993-LinLC #process: Intelligent Keyboard Layout Process (CCL, TZL, FSC), pp. 1070–1074.
HCI-SHI-1993-ZhanBR #design #semantics: Screen Layout and Semantic Structure in Iconic Menu Design (PZ, RRB, MWR), pp. 146–151.
DAC-1993-MogakiSKH #approach: Cooperative Approach to a Practical Analog LSI Layout System (MM, YS, MK, TH), pp. 544–549.
DAC-1993-NouraniP #algorithm #estimation: A Layout Estimation Algorithm for RTL Datapaths (MN, CAP), pp. 285–291.
DAC-1993-PanDL #constraints #graph #reduction: Optimal Graph Constraint Reduction for Symbolic Layout Compaction (PP, SkD, CLL), pp. 401–406.
DAC-1993-WanG #named: ABLE: AMD Backplane for Layout Engines (KWW, RAG), pp. 556–560.
SEKE-1992-SugiharaYM #automation #diagrams #specification: Automatic Layout of Diagrams for Software Specification (KS, KY, IM), pp. 245–252.
SEKE-1992-TaT #algorithm: Layout Algorithms for DFD Processors (KPT, TCT), pp. 567–573.
DAC-1992-Frankle #adaptation: Iterative and Adaptive Slack Allocation for Performance-Driven Layout and FPGA Routing (JF), pp. 536–542.
DAC-1992-KimLS #graph #modelling #using: A New Hierarchical Layout Compactor Using Simplified Graph Models (WK, JL, HS), pp. 323–326.
DAC-1992-LiaoC #synthesis: Routing Considerations in Symbolic Layout Synthesis (YL, SC), pp. 682–686.
DAC-1992-OkudaO #algorithm #generative #performance: An Efficient Routing Algorithm for SOG Cell Generation on a Dense Gate-Isolated Layout Style (RO, SO), pp. 676–681.
DAC-1991-BenkoskiS #synthesis #verification: The Role of Timing Verification in Layout Synthesis (JB, AJS), pp. 612–619.
DAC-1991-Gad-El-KarimG #generative #performance: Generation of Performance Sensitivities for Analog Cell Layout (GGEK, RSG), pp. 500–505.
DAC-1991-Harrison #using: VLSI Layout Compaction Using Radix Priority Search Trees (AJH), pp. 732–735.
DAC-1991-HwangHLH #automation #generative #performance: An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation (CYH, YCH, YLL, YCH), pp. 481–486.
DAC-1991-Kozminski #benchmark #evolution #metric #synthesis: Benchmarks for Layout Synthesis — Evolution and Current Status (KK), pp. 265–270.
DAC-1991-Luk #constraints #generative #performance #physics: A Fast Physical Constraint Generator for Timing Driven Layout (WKL), pp. 626–631.
DAC-1991-MogakiKSY #constraints: A Layout Improvement Method Based on Constraint Propagation for Analog LSI’s (MM, NK, NS, YY), pp. 510–513.
DAC-1991-OnoderaTT #bound: Branch-and-Bound Placement for Building Block Layout (HO, YT, KT), pp. 433–439.
DAC-1991-PedramB: Layout Driven Technology Mapping (MP, NBB), pp. 99–105.
DAC-1991-Wang #novel: Novel Routing Schemes for IC Layout, Part I: Two-Layer Channel Routing (DCW), pp. 49–53.
ICLP-1991-WatanabeK #parallel #problem: Co-operative Hierarchical Layout Problem Solver on Parallel Inference Machine (TW, KK), p. 892.
GG-1990-Brandenburg #approach #graph grammar: Layout Graph Grammars: The Placement Approach (FJB), pp. 144–156.
CHI-1990-BohringerP #algorithm #automation #constraints #graph #using: Using constraints to achieve stability in automatic graph layout algorithms (KFB, FNP), pp. 43–51.
PLDI-1990-PughW #inheritance #multi: Two-Directional Record Layout for Multiple Inheritance (WP, GEW), pp. 85–91.
DAC-1990-BowerSW #framework #generative #industrial: A Framework for Industrial Layout Generators (WB, CS, WW), pp. 419–424.
DAC-1990-CaiNSM #assembly #performance: A Data Path Layout Assembler for High Performance DSP Circuits (HC, SN, PS, HDM), pp. 306–311.
DAC-1990-CaiW #algorithm: A Channel/Switchbox Definition Algorithm for Building-Block Layout (YC, DFW), pp. 638–641.
DAC-1990-Domic #synthesis: Layout Synthesis of MOS Digital Cells (AD), pp. 241–245.
DAC-1990-Hojati #optimisation: Layout Optimization by Pattern Modification (RH), pp. 632–637.
DAC-1990-HsiehHLH #generative #named: LiB: A Cell Layout Generator (YCH, CYH, YLL, YCH), pp. 474–479.
DAC-1990-MatsumotoWUSHM #generative: Datapath Generator Based on Gate-Level Symbolic Layout (NM, YW, KU, YS, HH, SM), pp. 388–393.
DAC-1990-Onozawa #constraints: Layout Compaction with Attractive and Repulsive Constraints (AO), pp. 369–374.
DAC-1990-SaabR #effectiveness #evolution #heuristic #performance #probability #problem: Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout Problems (YS, VBR), pp. 26–31.
DAC-1990-SinghC #matrix #order: A Transistor Reordering Technique for Gate Matrix Layout (US, CYRC), pp. 462–467.
DAC-1990-SutanthavibulS #adaptation: An Adaptive Timing-Driven Layout for High Speed VLSI (SS, ES), pp. 90–95.
DAC-1990-TeraiTS #algorithm #assurance #constraints #design: A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint (MT, KT, KS), pp. 96–102.
DAC-1990-Wang: Pad Placement and Ring Routing for Custom Chip Layout (DCW), pp. 193–199.
CHI-1989-IwaiDYFT #architecture #automation #documentation #using: A document layout system using automatic document architecture extraction (II, MD, KY, MF, YT), pp. 369–374.
DAC-1989-AdamsS #generative: Template Style Considerations for Sea-of-Gates Layout Generation (GDA, CHS), pp. 31–36.
DAC-1989-ChenC #automation: The Layout Synthesizer: An Automatic Netlist-to-Layout System (CCC, SLC), pp. 232–238.
DAC-1989-HedenstiernaJ #design #using: The Use of Inverse Layout Trees for Hierarchical Design Rule Checking (NH, KOJ), pp. 508–512.
DAC-1989-IrwinO #2d #comparison #matrix #tool support: A Comparison of Four Two-dimensional Gate Matrix Layout Tools (MJI, RMO), pp. 698–701.
DAC-1989-LinDY #2d #matrix #synthesis: Gate Matrix Layout Synthesis with Two-Dimensional Folding (IL, DHCD, SHCY), pp. 37–42.
DAC-1989-Lo #automation #generative: Automatic Tub Region Generation for Symbolic Layout Compaction (CYL), pp. 302–306.
DAC-1989-LukD #multi #optimisation: Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout (WKL, AAD), pp. 110–115.
DAC-1989-Marple #optimisation: Transistor Size Optimization in the Tailor Layout System (DM), pp. 43–48.
DAC-1989-MilsomSCMAS #named #simulation: FACET: A CAE System for RF Analogue Simulation Including Layout (RFM, KJS, SGC, JCM, SA, FNS), pp. 622–625.
DAC-1989-PreasPC #automation #hybrid: Automatic Layout of Silicon-on-Silicon Hybrid Packages (BP, MP, DC), pp. 394–399.
DAC-1989-ShinL #2d #algorithm #performance: An Efficient Two-Dimensional Layout Compaction Algorithm (HS, CYL), pp. 290–295.
DAC-1989-TheWC: VIA Minimization by Layout Modification (KST, DFW, JC), pp. 799–802.
DAC-1989-TrickD #behaviour #named #synthesis #tool support: LASSIE: Structure to Layout for Behavioral Synthesis Tools (MTT, SWD), pp. 104–109.
DAC-1989-WaterkampWBRS: Technology Tracking of Non Manhattan VLSI Layout (JW, RW, RB, MR, GS), pp. 296–301.
DAC-1989-WeninVCLG #rule-based #verification: Rule-based VLSI Verification System Constrained by Layout Parasitics (JW, JV, MVC, JL, PG), pp. 662–667.
DAC-1988-BarthMS #named: Patchwork: Layout from Schematic Annotations (RB, LM, BS), pp. 250–255.
DAC-1988-Boyer #bibliography #perspective: Symbolic Layout Compaction Review (DGB), pp. 383–389.
DAC-1988-Cai88a: Connectivity Biased Channel Construction and Ordering for Building-Block Layout (HC), pp. 560–565.
DAC-1988-ChenB: A Module Area Estimator for VLSI Layout (XC, MLB), pp. 54–59.
DAC-1988-HenkelG #named #set #verification: RISCE — A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification (VH, UG), pp. 465–470.
DAC-1988-MarpleSH #performance: An Efficient Compactor for 45° Layout (DM, MS, HH), pp. 396–402.
DAC-1988-ObermeierK #physics: An Electrical Optimizer that Considers Physical Layout (FWO, RHK), pp. 453–459.
DAC-1988-OgawaTK #automation: Automatic Layout Procedures for Serial Routing Devices (YO, HT, TK), pp. 642–645.
DAC-1987-ApteK #standard: Strip Layout: A New Layout Methodology for Standard Circuit Modules (JA, GK), pp. 363–369.
DAC-1987-ChangCH #approach #automation #generative #matrix #using: Automated Layout Generation Using Gate Matrix Approach (YCC, SCC, LHH), pp. 552–558.
DAC-1987-DaiSK #performance #representation: A Dynamic and Efficient Representation of Building-Block Layout (WWMD, MS, ESK), pp. 376–384.
DAC-1987-Elias #case study #compilation #generative #re-engineering: A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator (NJE), pp. 82–88.
DAC-1987-Koeppe #fault: Optimal Layout to Avoid CMOS Stuck-Open Faults (SK), pp. 829–835.
DAC-1987-LinG #named: LES: A Layout Expert System (YLSL, DG), pp. 672–678.
DAC-1987-LueM #game studies #named: PLAY: Pattern-Based Symbolic Cell Layout: Part I: Transistor Placement (WJL, LPM), pp. 659–665.
DAC-1987-MaiaszH #functional #optimisation: Layout Optimization of CMOS Functional Cells (RLM, JPH), pp. 544–551.
DAC-1987-Preas #benchmark #metric: Benchmarks for Cell-Based Layout Systems (BP), pp. 319–320.
DAC-1986-BootehsazC #approach #independence: A technology independent approach to hierarchical IC layout extraction (AB, RAC), pp. 425–431.
DAC-1986-ClarkeF #geometry #named #recursion: Escher — a geometrical layout system for recursively defined circuits (EMC, YF), pp. 650–653.
DAC-1986-DeJesusCW #named #power management: PEARL: an expert system for power supply layout (EJD, JPC, CRW), pp. 615–621.
DAC-1986-FreemanKLN #automation #matrix #modelling: Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning (RDF, SMK, CGLH, MLN), pp. 418–424.
DAC-1986-FrisonG #editing #metaprogramming #named: MADMACS: a new VLSI layout macro editor (PF, EG), pp. 654–658.
DAC-1986-Hartoog #analysis #standard: Analysis of placement procedures for VLSI standard cell layout (MRH), pp. 314–319.
DAC-1986-JustKJ #on the #problem #standard: On the relative placement and the transportation problem for standard-cell layout (KMJ, JMK, FMJ), pp. 308–313.
DAC-1986-KrekelbergSSL #automation #compilation #synthesis: Automated layout synthesis in the YASC silicon compiler (DEK, ES, GES, LSL), pp. 447–453.
DAC-1986-LinA #bound #named: Minplex — a compactor that minimizes the bounding rectangle and individual rectangles in a layout (SLL, JA), pp. 123–130.
DAC-1986-VenkataramanW #automation #named: GEMS: an automatic layout tool for MIMOLA schematics (VVV, CDW), pp. 131–137.
DAC-1985-AnwayFR: PLINT layout system for VLSI chips (HA, GF, RR), pp. 449–452.
DAC-1985-BursteinY #design: Timing influenced layout design (MB, MNY), pp. 124–130.
DAC-1985-ChuL #design #tool support: Technology tracking for VLSI layout design tools (KCC, YEL), pp. 279–285.
DAC-1985-Cory #named: Layla: a VLSI layout language (WEC), pp. 245–251.
DAC-1985-HsuTCPT #named #standard: ALPS2: a standard cell layout system for double-layer metal technology (CPH, BNT, KC, RAP, JT), pp. 443–448.
DAC-1985-Marek-Sadowska #2d: Two-dimensional router for double layer layout (MMS), pp. 117–123.
DAC-1985-NodaYFKKF #algorithm #array #automation: Automatic layout algorithms for function blocks of CMOS gate arrays (SN, HY, EF, HK, HK, TF), pp. 46–52.
DAC-1985-Rosenberg: Auto-interactive schematics to layout translation (JBR), pp. 82–87.
DAC-1985-SaucierT: Systematic and optimized layout of MOS cells (GS, GT), pp. 53–61.
DAC-1985-SpiraH #array #hardware: Hardware acceleration of gate array layout (PMS, CH), pp. 359–366.
DAC-1985-TaylorBS #design #lessons learnt: Layout design-lessons from the Jedi designer (SLT, RB, TS), p. 337.
DAC-1984-ChenK #design #problem: The channel expansion problem in layout design (RRC, YK), pp. 388–391.
DAC-1984-DunlopADJKW #optimisation #using: Chip layout optimization using critical path weighting (AED, VDA, DND, MFJ, PK, MW), pp. 133–136.
DAC-1984-KozawaMT #algorithm #logic #top-down: Combine and top down block placement algorithm for hierarchical logic VLSI layout (TK, CM, HT), pp. 667–669.
DAC-1984-LotvinJG #named: Amoeba: A symbolic VLSI layout system (ML, BJ, RG), pp. 294–300.
DAC-1984-Marvik #verification: A method for IC layout verification (OAM), pp. 708–709.
DAC-1984-Mori #interactive: Interactive compaction router for VLSI layout (HM), pp. 137–143.
DAC-1984-OusterhoutHMST #named: Magic: A VLSI layout system (JKO, GTH, RNM, WSS, GST), pp. 152–159.
DAC-1984-OzakiWKIS #named: MGX: An integrated symbolic layout system for VLSI (MO, MW, MK, MI, KS), pp. 572–579.
DAC-1984-Smith #tool support #what: Basic turorial layout tools — what really is there (RS), p. 219.
DAC-1984-TienTCCE #array #automation #named: GALA — an automatic layout system for high density CMOS gate arrays (BNT, BST, JC, KSKC, SCE), pp. 657–662.
DAC-1984-Wagner #verification: Hierarchical layout verification (TJW), pp. 484–489.
DAC-1984-WieclawskiP #compilation #network #optimisation: Optimization of negative gate networks realized in weinberger-LIKF layout in a boolean level silicon compiler (AW, MAP), pp. 703–704.
STOC-1984-Blum #trade-off: An Area-Maximum Edge Length Tradeoff for VLSI Layout (NB), pp. 92–97.
DAC-1983-Barke #verification: A layout verification system for analog bipolar integrated circuits (EB), pp. 353–359.
DAC-1983-KedemW: Graph-optimization techniques for IC layout and compaction (GK, HW), pp. 113–120.
DAC-1983-LiaoW #algorithm #constraints: An algorithm to compact a VLSI symbolic layout with mixed constraints (YZL, CKW), pp. 107–112.
DAC-1983-MayoO: Pictures with parentheses: Combining graphics and procedures in a VLSI layout tool (RNM, JKO), pp. 270–276.
DAC-1983-Robinson #array #automation: Automatic layout for gate arrays with one layer of metal (PR0), pp. 658–664.
DAC-1983-Smith #independence: Technology-independent circuit layout (RJSI), pp. 390–393.
DAC-1983-SmithNBSW #array #automation #geometry #named: VGAUA: The Variable Geometry Automated Universal Array layout System (DCS, RN, FB, SSS, JCW), pp. 425–429.
DAC-1983-Supowit #standard: Reducing channel density in standard cell layout (KJS), pp. 263–269.
DAC-1983-TamuraON #analysis: Path delay analysis for hierarchical building block layout system (ET, KO, TN), pp. 403–410.
DAC-1982-AdachiKNS #design #top-down: Hierarchical top-down layout design method for VLSI chip (TA, HK, MN, TS), pp. 785–791.
DAC-1982-ArnoldO #approach #geometry #named: Lyra: A new approach to geometric layout rule checking (MHA, JKO), pp. 530–536.
DAC-1982-BeylsHLMP #design #tool support: A design methodology based upon symbolic layout and integrated cad tools (AMB, BH, JL, GM, AP), pp. 872–878.
DAC-1982-Hassett #approach #automation #problem: Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI (JEH), pp. 777–784.
DAC-1982-InoueAF #design #precise: A layout system for high precision design of progressive die (KI, MA, TF), pp. 246–252.
DAC-1982-KangKL #adaptation #cpu #design #evolution #logic #matrix #random: Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design (SMK, RHK, HFSL), pp. 170–174.
DAC-1982-LieH: A bus router for IC layout (ML, CSH), pp. 129–132.
DAC-1982-LuhukayK #synthesis: A layout synthesis system for NMOS gate-cells (JFPL, WJK), pp. 307–314.
DAC-1982-MatsudaFTMNKG #design #low cost #named: LAMBDA: A quick, low cost layout design system for master-slice LSI s (TM, TF, KT, HM, HN, FK, SG), pp. 802–808.
DAC-1982-MudgeRLA #image #validation: Cellular image processing techniques for VLSI circuit layout validation and routing (TNM, RAR, RML, DEA), pp. 537–543.
DAC-1982-TeraiKSY: A consideration of the number of horizontal grids used in the routing of a masterslice layout (MT, HK, KS, TY), pp. 121–128.
DAC-1982-ToddHPBGAB #array #multi: CGALA-a multi technology Gate Array Layout system (LFT, JMH, SVP, JLB, DJG, RJA, AKB), pp. 792–801.
DAC-1982-WipflerWM #algorithm: A combined force and cut algorithm for hierarchical VLSI layout (GJW, MW, DAM), pp. 671–677.
STOC-1982-Leighton: A Layout Strategy for VLSI which Is Provably Good (FTL), pp. 85–98.
DAC-1981-AblasserJ #recognition #verification: Circuit recognition and verification based on layout information (IA, UJ), pp. 684–689.
DAC-1981-BradyS #optimisation #verification: Verification and optimization for LSI & PCB layout (HNB, RJSI), pp. 365–371.
DAC-1981-ChibaOKNIK #named: SHARPS: A hierarchical layout system for VLSI (TC, NO, TK, IN, TI, SK), pp. 820–827.
DAC-1981-EdmondsonJ #low cost #verification: A low cost hierarchical system for VLSI layout and verification (THE, RMJ), pp. 505–510.
DAC-1981-GoatesP #array #design #lisp #logic #modelling #named: ABLE: A LISP-based layout modeling language with user-definable procedural models for storage/logic array design (GBG, SSP), pp. 322–329.
DAC-1981-HorngL #automation #interactive: An automatic/interactive layout planning system for arbitrarily-sized rectangular building blocks (CSH, ML), pp. 293–300.
DAC-1981-PerskyES #automation: The Hughes Automated Layout System — automated LSI/VLSI layout based on channel routing (GP, CE, DMS), pp. 22–28.
DAC-1981-RothermelM #power management: Computation of power supply nets in VLSI layout (HJR, DAM), pp. 37–42.
DAC-1981-SatoNTSOY #named: MILD — A cell-based layout system for MOS-LSI (KS, TN, MT, HS, MO, TY), pp. 828–836.
DAC-1981-TanakaMTYOTKT #array #design: An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3 (CT, SM, HT, TY, KO, MT, RK, MT), pp. 812–819.
DAC-1981-Trimberger #interactive: Combining graphics and a layout language in a single interactive system (ST), pp. 234–239.
DAC-1981-Weste #grid: Virtual grid symbolic layout (NW), pp. 225–233.
DAC-1981-Williams #automation #verification: Automatic VLSI layout verification (LW), pp. 726–732.
DAC-1980-ChaoHY #approach #consistency: A hierarchical approach for layout versus circuit consistency check (SPC, YSH, LMY), p. 269.
DAC-1980-ChaoHY80a #approach #consistency: A hierarchical approach for layout versus circuit consistency check (SPC, YSH, LMY), pp. 270–276.
DAC-1980-McGrathW #design #verification: Design integrity and immunity checking: A new look at layout verification and design rule checking (EJM, TW), pp. 263–268.
DAC-1980-ShirakawaOHTO #logic #random: A layout system for the random logic portion of MOS LSI (IS, NO, TH, ST, HO), pp. 92–99.
DAC-1980-SoukupR #representation: Cell map representation for hierarchical layout (JS, JR), pp. 591–594.
DAC-1980-SzepieniecO #approach #problem: The genealogical approach to the layout problem (AAS, RHJMO), pp. 535–542.
STOC-1980-FischerP: Optimal Tree Layout (MJF, MP), pp. 177–189.
DAC-1979-BekeS #automation #interactive #named: CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI (HB, WS), pp. 102–108.
DAC-1979-Chang #recognition #using: LSI layout checking using bipolar device recognition technique (CSC), pp. 95–101.
DAC-1979-Goto #2d #algorithm #problem #slicing: A two-dimensional placement algorithm for the master slice LSI layout problem (SG), pp. 11–17.
DAC-1979-Johnson79a: PC board layout techniques (DRJ), pp. 337–343.
DAC-1979-SaharaKN #interactive: An interactive layout system of analog printed wiring boards (KiS, KiK, IN), pp. 506–512.
DAC-1979-SatoNSY #design #named: MIRAGE — a simple-model routing program for the hierarchical layout design of IC masks (KS, TN, HS, TY), pp. 297–304.
DAC-1979-UeharaC #array #functional: Optimal layout of CMOS functional arrays (TU, WMvC), pp. 287–289.
DAC-1979-Wilmore #database #design #interactive #performance: The design of an efficient data base to support an interactive LSI layout system (JAW), pp. 445–451.
DAC-1978-BayeganA #design #editing #interactive #logic #simulation: An integrated system for interactive editing of schematics, logic simulation and PCB layout design (HMB, EJA), pp. 1–8.
DAC-1978-FairbairnR #interactive #named: ICARUS: An interactive integrated circuit layout program (DGF, JAR), pp. 188–192.
DAC-1978-PreasG #automation: Methods for hierarchical automatic layout of custom LSI circuit masks (BP, CWG), pp. 206–212.
DAC-1978-Ruch #approach #graph #interactive: Interactive space layout: A graph theoretical approach (JR), pp. 152–157.
DAC-1977-BedardFSS: A production PCB layout system on a minicomputer (KB, SF, BS, US), pp. 168–173.
DAC-1977-ChenFKNS #automation #problem: The chip layout problem: An automatic wiring procedure (KAC, MF, KHK, NN, SS), pp. 298–302.
DAC-1977-ChoKS #approach #automation #design #named: Floss: An approach to automated layout for high-volume designs (YEC, AJK, DES), pp. 138–141.
DAC-1977-KhokhaniP #problem: The chip layout problem: A placement procedure for lsi (KHK, AMP), pp. 291–297.
DAC-1977-Larsen #effectiveness: Cost effective layout digitizing and mask pen plotting of custom microelectronic devices (RPL), pp. 386–390.
DAC-1977-NishiokaKN #automation: A minicomputerized automatic layout system for two-layer printed wiring boards (IN, TK, HN), pp. 1–11.
DAC-1977-YoshidaMNCON #scalability: A layout checking system for large scale integrated circuits (KY, TM, YN, TC, KO, SN), pp. 322–330.
DAC-1976-Cleemput #aspect-oriented #on the #problem: On the topological aspects of the circuit layout problem (WMvC), pp. 441–450.
DAC-1976-Feller #automation #low cost: Automatic layout of low-cost quick-turnaround random-logic custom LSI devices (AF), pp. 79–85.
DAC-1976-GibsonN #named: SLIC — Symbolic Layout of Integrated Circuits (DG, SN), pp. 434–440.
DAC-1976-Persky #automation #named #string: PRO — an automatic string placement program for polycell layout (GP), pp. 417–424.
DAC-1976-RabideauF #interactive: Interactive graphics package for human engineering and layout of vehicle workspace (GFR, JF), pp. 34–41.
DAC-1976-Schweikert #2d #algorithm: A 2-dimensional placement algorithm for the layout of electrical circuits (DGS), pp. 408–416.
DAC-1975-ChienSTR #design: A computer-aided minimum cost transfer machine layout design (TTC, SS, WAT, PR), pp. 202–209.
DAC-1975-GiuglianoB #automation #design: Present and future on P.C.B. layout design automation system at SIT-Siemens (AG, FB), pp. 134–143.
DAC-1975-Valle #relational: Relational data handling techniques in integrated circuit mask layout procedures (GV), pp. 407–413.
DAC-1975-Welt #named: NOMAD: A printed wiring board layout system (MJW), pp. 152–161.
DAC-1974-CalafioreF #multi: A system for multilayer printed wiring layout (RLC, JCF), pp. 322–326.
DAC-1974-CleemputL #formal method #graph #problem: An improved graph-theoretic model for the circuit layout problem (WMvC, JGL), pp. 82–90.
DAC-1974-KozawaHISS #automation #generative: Advanced LILAC — an Automated Layout Generation system for MOS/LSIs (TK, HH, TI, JS, SS), pp. 26–46.
DAC-1972-FrewR #approach #problem: Building polyonimoes; an approach to the space layout problem (RSF, PHR), p. 238.
DAC-1972-Harvey #automation: Automated board layout (JGH), pp. 264–271.
DAC-1971-LarsenM #clustering #equation #logic: Partitioning and ordering of logic equations for optimum MOS LSI device layout (RPL, LM), pp. 131–142.
DAC-1971-White #named: RELATE: Relationship layout technique (RNW), p. 221.
DAC-1970-AkersGR: IC mask layout with a single conductor layer (SBA, JMG, DLR), pp. 7–16.
DAC-1970-SassK #evaluation #logic: An 1130-based logic, layout and evaluation system (WHS, SPK), pp. 64–70.
DAC-1970-Smith: Computer-assisted template layout (KES), pp. 145–157.
DAC-1968-KadisTVHG #source code: Building block programs for the layout of printed circuit boards utilizing integrated circuit packs (DAPSYS V.2) (RWK, KLT, WJVJ, WLH, CEG).
DAC-1968-Martin #design: Computer-aided circuit layout and design (LCM).
DAC-1968-Silverberg #named: CLIC — computer layout of integrated circuits (MS).
SHARE-1965-FiskI #automation #quote: “ACCEL”: automated circuit card etching layout (CJF, DDI).