Travelled to:15 × USA
2 × Germany
4 × France
Collaborated with:∅ I.L.Markov S.Krishnaswamy A.Alaghi G.F.Viamontes T.Chen C.Yu F.Gao A.Gupta R.D.Blanton K.Chakrabarty M.J.Batek R.L.Maziasz R.L.Maiasz M.Kawai A.Goundan C.Li D.V.Campenhout T.N.Mudge H.Yalcin R.Palermo M.Mortazavi C.Bamji K.A.Sakallah E.J.Marinissen D.Y.Lee C.Sellathamby B.Moore S.Slupsky L.Pujol
Talks about:circuit (9) logic (5) stochast (4) fault (4) test (4) cmos (4) method (3) design (3) applic (3) simul (3)
Person: John P. Hayes
DBLP: Hayes:John_P=
Contributed to:
2015
201420132011200920092008200520052004200320011999199719971994199219911987198419821976Wrote 23 papers:
- DAC-2015-ChenH #equivalence #logic #probability
- Equivalence among stochastic logic circuits and its application (THC, JPH), p. 6.
- DAC-2015-Hayes #challenge #probability
- Introduction to stochastic computing and its challenges (JPH), p. 3.
- DATE-2014-AlaghiH #performance #probability #using
- Fast and accurate computation using stochastic circuits (AA, JPH), pp. 1–4.
- DAC-2013-AlaghiLH #probability #realtime
- Stochastic circuits for real-time image-processing applications (AA, CL, JPH), p. 6.
- DATE-2011-YuH #fault #logic
- Trigonometric method to handle realistic error probabilities in logic circuits (CCY, JPH), pp. 64–69.
- DAC-2009-KrishnaswamyMH #testing
- Improving testability and soft-error resilience through retiming (SK, ILM, JPH), pp. 508–513.
- DATE-2009-MarinissenLHSMSP #question #testing
- Contactless testing: Possibility or pipe-dream? (EJM, DYL, JPH, CS, BM, SS, LP), pp. 676–681.
- DAC-2008-KrishnaswamyMH #design #logic #on the #reliability
- On the role of timing masking in reliable logic circuit design (SK, ILM, JPH), pp. 924–929.
- DAC-2005-GaoH #multi #reduction
- Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages (FG, JPH), pp. 31–36.
- DATE-2005-KrishnaswamyVMH #evaluation #matrix #probability #reliability
- Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices (SK, GFV, ILM, JPH), pp. 282–287.
- DATE-v2-2004-ViamontesMH #quantum #simulation
- High-Performance QuIDD-Based Simulation of Quantum Circuits (GFV, ILM, JPH), pp. 1354–1355.
- DAC-2003-Hayes #concept #named #quantum #tutorial
- Tutorial: basic concepts in quantum circuits (JPH), p. 893.
- DAC-2001-YalcinPMBSH #dependence #using
- An Advanced Timing Characterization Method Using Mode Dependency (HY, RP, MM, CB, KAS, JPH), pp. 657–660.
- DAC-1999-CampenhoutMH #design #generative #pipes and filters #testing #verification
- High-Level Test Generation for Design Verification of Pipelined Microprocessors (DVC, TNM, JPH), pp. 185–188.
- DAC-1997-GuptaH #2d #generative #layout #named #optimisation
- CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells (AG, JPH), pp. 452–455.
- EDTC-1997-BlantonH #fault
- The input pattern fault model and its application (RDB, JPH), p. 628.
- DAC-1994-ChakrabartyH #named #testing
- DFBT: A Design-for-Testability Method Based on Balance Testing (KC, JPH), pp. 351–357.
- DAC-1992-BatekH #logic
- Test-Set Preserving Logic Transformations (MJB, JPH), pp. 454–458.
- DAC-1991-MaziaszH
- Exact Width and Height Minimization of CMOS Cells (RLM, JPH), pp. 487–493.
- DAC-1987-MaiaszH #functional #layout #optimisation
- Layout Optimization of CMOS Functional Cells (RLM, JPH), pp. 544–551.
- DAC-1984-KawaiH #fault #simulation
- An experimental MOS fault simulation program CSASIM (MK, JPH), pp. 2–9.
- DAC-1982-Hayes #fault #simulation
- A fault simulation methodology for VLSI (JPH), pp. 393–399.
- DAC-1976-GoundanH #clustering #fault #logic
- Partitioning logic circuits to maximize fault resolution (AG, JPH), pp. 271–277.