BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
2 × USA
Collaborated with:
F.Özgüner D.W.Marhefka J.DeGroat J.Stofer L.Hanrahan J.A.Walter J.Leenstra G.Döttling B.Leppla H.Münster K.W.Kark
Talks about:
verif (2) multiprocessor (1) forgotten (1) hierarch (1) approach (1) random (1) design (1) teach (1) simul (1) logic (1)

Person: Bruce Wile

DBLP DBLP: Wile:Bruce

Contributed to:

DAC 20012001
DAC 19971997

Wrote 2 papers:

DAC-2001-OzgunerMDWSH #design #education #logic #verification
Teaching Future Verification Engineers: The Forgotten Side of Logic Design (, DWM, JD, BW, JS, LH), pp. 253–255.
DAC-1997-WalterLDLMKW #approach #multi #random #simulation #verification
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors (JAW, JL, GD, BL, HJM, KWK, BW), pp. 89–94.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.