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Travelled to:
1 × France
Collaborated with:
A.Lu H.Lu E.Jang Y.Lin C.Hung R.Lin
Talks about:
transistor (1) placement (1) standard (1) simultan (1) pair (1) cmos (1) cell (1)

Person: Chun-Chih Chuang

DBLP DBLP: Chuang:Chun=Chih

Contributed to:

DATE 20152015

Wrote 1 papers:

DATE-2015-LuLJLHCL #standard
Simultaneous transistor pairing and placement for CMOS standard cells (AL, HJL, EJJ, YPL, CHH, CCC, RBL), pp. 1647–1652.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.