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Travelled to:
1 × France
Collaborated with:
S.Pullela R.Panda A.Dharchoudhury
Talks about:
circuit (1) combin (1) taper (1) stage (1) wise (1) size (1) cmos (1)

Person: Gopal Vija

DBLP DBLP: Vija:Gopal

Contributed to:

DATE 19981998

Wrote 1 papers:

DATE-1998-PullelaPDV
CMOS Combinational Circuit Sizing by Stage-wise Tapering (SP, RP, AD, GV), pp. 985–986.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.