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Travelled to:
2 × USA
Collaborated with:
∅ T.Lemeunier R.Mayr
Talks about:
transistor (1) function (1) abstract (1) scheme (1) verif (1) layer (1) fpgas (1) doubl (1) array (1) wire (1)

Person: Guy Dupenloup

DBLP DBLP: Dupenloup:Guy

Contributed to:

DAC 20062006
DAC 19841984

Wrote 2 papers:

DAC-2006-DupenloupLM #abstraction #functional #verification
Transistor abstraction for the functional verification of FPGAs (GD, TL, RM), pp. 1069–1072.
DAC-1984-Dupenloup #array
A wire routing scheme for double-layer cell arrays (GD), pp. 32–37.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.