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Travelled to:
1 × France
Collaborated with:
J.Rigaud L.Fesquet M.Renaudin
Talks about:
asynchron (1) communic (1) system (1) design (1) model (1) level (1) arbit (1) high (1) chip (1)

Person: Jerome Quartana

DBLP DBLP: Quartana:Jerome

Contributed to:

DATE 20022002

Wrote 1 papers:

DATE-2002-RigaudFRQ #communication #design #modelling
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems (JBR, LF, MR, JQ), p. 1090.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.