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Travelled to:
1 × France
2 × Germany
Collaborated with:
M.Renaudin A.Cherkaoui V.Fischer A.Aubert N.Huot H.Dubreuil J.Rigaud J.Quartana
Talks about:
asynchron (2) ring (2) architectur (1) comparison (1) communic (1) entropi (1) system (1) invert (1) design (1) style (1)

Person: Laurent Fesquet

DBLP DBLP: Fesquet:Laurent

Contributed to:

DATE 20122012
DATE 20052005
DATE 20022002

Wrote 3 papers:

DATE-2012-CherkaouiFAF #comparison #self
Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs (AC, VF, AA, LF), pp. 1325–1330.
DATE-2005-HuotDFR #architecture #logic #multi
FPGA Architecture for Multi-Style Asynchronous Logic (NH, HD, LF, MR), pp. 32–33.
DATE-2002-RigaudFRQ #communication #design #modelling
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems (JBR, LF, MR, JQ), p. 1090.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.