BibSLEIGH — Proceedings of the Seventh Conference on Design, Automation and Test in Europe

Proceedings of the Seventh Conference on Design, Automation and Test in Europe
DATE, 2002.

SYS

@proceedings{DATE-2002,
	address       = "Paris, France",
	isbn          = "0-7695-1471-5",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the Seventh Conference on Design, Automation and Test in Europe}",
	year          = 2002,
}

Contents (228 items)

DATE-2002-Man #complexity #integration #on the: On Nanoscale Integration and Gigascale Complexity in the Post.Com World (HDM), p. 12.
DATE-2002-Scanlon #design: Global Responsibilities in SOC Design (TS), p. 12.
DATE-2002-Phillips #embedded #how: How to Choose Semiconductor IP? — Embedded Processor (IP), p. 14.
DATE-2002-Ratford #design #memory management: Make Your SoC Design a Winner: Select the Right Memory IP (VR), p. 15.
DATE-2002-Martin #embedded #how: How to Choose Semiconductor IP: Embedded Software (GM), p. 16.
DATE-2002-Bricaud #how #question: IP Day: How to Choose Semiconductor IP? (PB), p. 17.
DATE-2002-KaivolaN #float #multi #verification: Formal Verification of the Pentium ® 4 Floating-Point Multiplier (RK, NN), pp. 20–27.
DATE-2002-Velev #similarity #using #verification: Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer (MNV), pp. 28–35.
DATE-2002-MishraDNT #automation #execution #functional #multi #pipes and filters #verification: Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units (PM, NDD, AN, HT), pp. 36–43.
DATE-2002-PenaCSP #case study #verification: A Case Study for the Verification of Complex Timed Circuits: IPCMOS (MAP, JC, ABS, EP), pp. 44–51.
DATE-2002-VicenteLH #combinator #optimisation: FPGA Placement by Thermodynamic Combinatorial Optimization (JdV, JL, RH), pp. 54–60.
DATE-2002-ZhuangKSJ: An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees (CZ, YK, KS, LJ), pp. 61–68.
DATE-2002-LinCC #using: Arbitrary Convex and Concave Rectilinear Module Packing Using TCG (JML, HLC, YWC), pp. 69–75.
DATE-2002-PronathGA #design #fault #float: A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits (MP, HEG, KA), pp. 78–83.
DATE-2002-PadmanabanT #fault #multi: Exact Grading of Multiple Path Delay Faults (SP, ST), pp. 84–88.
DATE-2002-Al-ArsG #fault #in memory #memory management #modelling #testing: Modeling Techniques and Tests for Partial Faults in Memory Devices (ZAA, AJvdG), pp. 89–93.
DATE-2002-LeeCDGM #algorithm #detection #fault #multi #testing: A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults (SL, BC, JD, MRG, MRM), pp. 94–99.
DATE-2002-BertozziBM #encoding #fault #power management: Low Power Error Resilient Encoding for On-Chip Data Buses (DB, LB, GDM), pp. 102–109.
DATE-2002-SimunicB #network #power management: Managing Power Consumption in Networks on Chip (TS, SPB), pp. 110–116.
DATE-2002-IraniGS #analysis #multi #power management: Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States (SI, RKG, SKS), pp. 117–123.
DATE-2002-PonomarevKG #estimation #named: AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors (DP, GK, KG), pp. 124–129.
DATE-2002-Essi #all about #implementation: IP is All About Implementation and Customer Satisfaction (VPEJ), p. 132.
DATE-2002-GoldbergPB #algorithm #problem #satisfiability #symmetry #using: Using Problem Symmetry in Search Based Satisfiability Algorithms (EIG, MRP, RKB), pp. 134–141.
DATE-2002-GoldbergN #named #performance #robust: BerkMin: A Fast and Robust Sat-Solver (EIG, YN), pp. 142–149.
DATE-2002-CabodiCQ #clustering #image #scheduling: Dynamic Scheduling and Clustering in Symbolic Image Computation (GC, PC, SQ), pp. 150–156.
DATE-2002-MacchiaruloMP #energy: Wire Placement for Crosstalk Energy Minimization in Address Buses (LM, EM, MP), pp. 158–162.
DATE-2002-KimR #power management #reduction #scalability: Dynamic VTH Scaling Scheme for Active Leakage Power Reduction (CHK, KR), pp. 163–167.
DATE-2002-AzevedoICGDVN #scheduling #using: Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints (AA, II, RC, RG, NDD, AVV, AN), pp. 168–175.
DATE-2002-MukherjeeWCM #component: Sizing Power/Ground Meshes for Clocking and Computing Circuit Components (AM, KW, LHC, MMS), pp. 176–183.
DATE-2002-VoorakaranamCC #agile #framework #testing: A Signature Test Framework for Rapid Production Testing of RF Circuits (RV, SC, AC), pp. 186–191.
DATE-2002-GuardianiMDSZXL #optimisation #testing: Analog IP Testing: Diagnosis and Optimization (CG, PM, LD, SS, SZ, WX, SL), pp. 192–196.
DATE-2002-Hoffmann #design #generative #testing: A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits (CH), pp. 197–204.
DATE-2002-LechugaMMB #detection #fault: Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal Ics (YL, RM, MM, SB), pp. 205–211.
DATE-2002-GhanmiGHMSS #paradigm #reuse: E-Design Based on the Reuse Paradigm (LG, AG, MH, BM, KS, GS), pp. 214–220.
DATE-2002-SchneiderDIRUMCG #collaboration #generative #testing: Internet-Based Collaborative Test Generation with MOSCITO (AS, KHD, EI, JR, RU, PM, TC, EG), pp. 221–226.
DATE-2002-KazmierskiC #design #distributed #framework: A Two-Tier Distributed Electronic Design Framework (TJK, NC), pp. 227–231.
DATE-2002-RettbergT #design #embedded: Embedded System Design Based On Webservices (AR, WT), pp. 232–236.
DATE-2002-GerousisLPPRS #framework #platform #question: Who Owns the Platform? (VG, OL, PGP, MP, CR, GS), p. 238.
DATE-2002-Nicolaidis #embedded #robust: IP for Embedded Robustness (MN), pp. 240–241.
DATE-2002-Pateras #embedded: Embedded Diagnosis IP (SP), pp. 242–243.
DATE-2002-DupontNR #embedded #robust: Embedded Robustness Ips (ED, MN, PR), pp. 244–245.
DATE-2002-GorenF #finite #heuristic #named #reduction #state machine: CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines (SG, FJF), pp. 248–254.
DATE-2002-ThorntonFRT #evaluation #self: Generalized Early Evaluation in Self-Timed Circuits (MAT, KF, RBR, CT), pp. 255–259.
DATE-2002-JungKK #logic #performance #synthesis: Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain (SOJ, KWK, SMK), pp. 260–265.
DATE-2002-DaemsGS #approach #linear #performance: A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics (WD, GGEG, WMCS), pp. 268–273.
DATE-2002-PoppOHB #analysis #automation #parametricity: Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits (RP, JO, LH, EB), pp. 274–278.
DATE-2002-VanasscheGS #behaviour #matrix #modelling #using: Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices (PV, GGEG, WMCS), pp. 279–284.
DATE-2002-CiesielskiKZR #canonical #diagrams #representation #verification: Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification (MJC, PK, ZZ, BR), pp. 285–289.
DATE-2002-GuarnieriCASHZ #question #tool support: EDA Tools for RF: Myth or Reality? (LG, EC, CA, SS, MH, XZ), pp. 292–293.
DATE-2002-LeeWH #design #implementation #multi #platform #runtime: Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs (TML, WW, JH), pp. 296–301.
DATE-2002-PaskoVS #c++ #design: Techniques to Evolve a C++ Based System Design Language (RP, SV, PS), pp. 302–309.
DATE-2002-GinesPRSM #behaviour #design #modelling #parametricity #reuse: A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects (AJG, EJP, AR, RS, NMM), pp. 310–314.
DATE-2002-RahajandraibeDACMC #parametricity: Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications (WR, CD, DA, BC, BM, VC), pp. 316–321.
DATE-2002-LampeL #optimisation #problem: Global Optimization Applied to the Oscillator Problem (SL, SL), pp. 322–326.
DATE-2002-BorelMJRRRRT: MEDEA+ and ITRS Roadmaps (JB, GM, AAJ, SR, MR, WR, IRH, FT), p. 328.
DATE-2002-ChelceaNBE #synthesis: A Burst-Mode Oriented Back-End for the Balsa Synthesis System (TC, SMN, AB, DAE), pp. 330–337.
DATE-2002-KhomenkoKY #detection #integer #programming #using: Detecting State Coding Conflicts in STGs Using Integer Programming (VK, MK, AY), pp. 338–345.
DATE-2002-HassounCC #verification: Verifying Clock Schedules in the Presence of Cross Talk (SH, ECG, CC), pp. 346–350.
DATE-2002-GoffioulWVD #analysis #approach #architecture #using: Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach (MG, PW, GV, SD), pp. 352–356.
DATE-2002-VandenbusscheLUSG #design: Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter (JV, EL, KU, MS, GGEG), pp. 357–361.
DATE-2002-CarmonaJDER #design #programmable: Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip (RCG, FJG, RDC, SEM, ÁRV), pp. 362–366.
DATE-2002-PandeyP #algorithm #architecture #design #generative #incremental #testing: An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs (ARP, JHP), pp. 368–375.
DATE-2002-BayraktarogluO #fault: Gate Level Fault Diagnosis in Scan-Based BIST (IB, AO), pp. 376–381.
DATE-2002-LiuCG #identification: An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment (CL, KC, MG), pp. 382–386.
DATE-2002-RedaO #encoding #testing: Reducing Test Application Time Through Test Data Mutation Encoding (SR, AO), pp. 387–393.
DATE-2002-MichelWWM #hardware #trade-off: Hardware/Software Trade-Offs for Advanced 3G Channel Coding (HM, AW, NW, MM), pp. 396–401.
DATE-2002-HalambiSBDN #compilation #performance #reduction #using: An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs (AH, AS, PB, NDD, AN), pp. 402–408.
DATE-2002-SteinkeWLM #energy #reduction: Assigning Program and Data Objects to Scratchpad for Energy Reduction (SS, LW, BSL, PM), pp. 409–415.
DATE-2002-MicheliB #design #network #paradigm: Networks on Chip: A New Paradigm for Systems on Chip Design (GDM, LB), pp. 418–419.
DATE-2002-WilliamsHA #communication #parallel: Communication Mechanisms for Parallel DSP Systems on a Chip (JW, NH, BDA), pp. 420–422.
DATE-2002-GoossensWPM #network: Networks on Silicon: Combining Best-Effort and Guaranteed Services (KGWG, PW, AMGP, JLvM), pp. 423–425.
DATE-2002-AchterenDCL #reuse: Data Reuse Exploration Techniques for Loop-Dominated Application (TVA, GD, FC, RL), pp. 428–435.
DATE-2002-KadayifKVIS #compilation #energy #estimation #framework #named #optimisation: EAC: A Compiler Framework for High-Level Energy Estimation and Optimization (IK, MTK, NV, MJI, AS), pp. 436–442.
DATE-2002-TangGN #embedded #power management: Power Savings in Embedded Processors through Decode Filer Cache (WT, RKG, AN), pp. 443–448.
DATE-2002-BeniniBMM #embedded #energy: Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors (LB, DB, AM, EM), pp. 449–453.
DATE-2002-BecerZBPH #analysis #using: Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model (MRB, VZ, DB, RP, INH), pp. 456–463.
DATE-2002-JerkeL #analysis #verification: Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits (GJ, JL), pp. 464–469.
DATE-2002-HuangTXWL #algorithm #polynomial #problem: A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem (LDH, XT, HX, DFW, IML), pp. 470–475.
DATE-2002-CotaCLO #design #testing: Test Planning and Design Space Exploration in a Core-Based Environment (ÉFC, LC, ML, AO), pp. 478–485.
DATE-2002-LiHCSWCCHL #design: A Hierarchical Test Scheme for System-On-Chip Designs (JFL, HJH, JBC, CPS, CWW, CC, SIC, CYH, HPL), pp. 486–490.
DATE-2002-IyengarCM #performance #scalability: Efficient Wrapper/TAM Co-Optimization for Large SOCs (VI, KC, EJM), pp. 491–498.
DATE-2002-BaldiniBPMT #functional #uml: Beyond UML to an End-of-Line Functional Test Engine (AB, AB, PP, SM, AT), pp. 499–503.
DATE-2002-RichterE #analysis #interface: Event Model Interfaces for Heterogeneous System Analysis (KR, RE), pp. 506–513.
DATE-2002-SchmitzAE #distributed #embedded #energy #scheduling: Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems (MTS, BMAH, PE), pp. 514–521.
DATE-2002-PaulT #approach #modelling #virtual machine: A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems (JMP, DET), pp. 522–528.
DATE-2002-MenardS #algorithm #automation #evaluation #fixpoint: Automatic Evaluation of the Accuracy of Fixed-Point Algorithms (DM, OS), pp. 529–535.
DATE-2002-BrockELSDBOK #design #power management: Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs (KB, CE, RL, US, AD, JB, DO, MK), p. 538.
DATE-2002-RizzoC #architecture #case study #configuration management #video: A Video Compression Case Study on a Reconfigurable VLIW Architecture (DR, OC), pp. 540–546.
DATE-2002-Sanchez-ElezFMMKHB #architecture #configuration management #multi: A Complete Data Scheduler for Multi-Context Reconfigurable Architectures (MSE, MF, RM, RH, NB, FJK), pp. 547–552.
DATE-2002-SassatelliTBGDCG #architecture #configuration management #scalability: Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications (GS, LT, PB, TG, CD, GC, JG), pp. 553–558.
DATE-2002-TeichK #configuration management #finite #implementation #self #state machine: (Self-)reconfigurable Finite State Machines: Theory and Implementation (JT, MK), pp. 559–566.
DATE-2002-AcarNP #framework #parametricity #simulation: A Linear-Centric Simulation Framework for Parametric Fluctuations (EA, SRN, LTP), pp. 568–575.
DATE-2002-DessoukyS #array #automation #generative: Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio (MD, DS), pp. 576–580.
DATE-2002-SchwenckerSPG #adaptation #parametricity #set #using #worst-case: Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets (RS, FS, MP, HEG), pp. 581–585.
DATE-2002-VandersteenWDV #evaluation #performance: High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions (GV, PW, SD, FV), pp. 586–590.
DATE-2002-KranitisPGZ #effectiveness #self: Effective Software Self-Test Methodology for Processor Cores (NK, AMP, DG, YZ), pp. 592–597.
DATE-2002-ChandraC #clustering #testing: Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression (AC, KC), pp. 598–603.
DATE-2002-GonciariAN #testing: Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression (PTG, BMAH, NN), pp. 604–611.
DATE-2002-FavalliM #fault #problem #self: Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths (MF, CM), pp. 612–617.
DATE-2002-YooNGJ #automation #design #generative #modelling #operating system #performance #simulation: Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design (SY, GN, LG, AAJ), pp. 620–627.
DATE-2002-ZhengPBK #analysis #modelling #scalability: Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses (HZ, LTP, MWB, BK), pp. 628–633.
DATE-2002-LiP #analysis #approach #modelling: A Linear-Centric Modeling Approach to Harmonic Balance Analysis (PL, LTP), pp. 634–639.
DATE-2002-PenzesM #energy #estimation: An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor (PIP, AJM), pp. 640–647.
DATE-2002-OttenCG #automation #design: Design Automation for Deepsubmicron: Present and Future (RHJMO, RC, PG), pp. 650–657.
DATE-2002-LewisBLWGT #configuration management #question #what: Reconfigurable SoC — What Will it Look Like? (JBL, IB, RL, CW, BG, YT), pp. 660–662.
DATE-2002-PandiniPS #logic #synthesis: Congestion-Aware Logic Synthesis (DP, LTP, AJS), pp. 664–671.
DATE-2002-KutzschebauchS #composition #layout: Layout Driven Decomposition with Congestion Consideration (TK, LS), pp. 672–676.
DATE-2002-SulimmaKNV #constant: Improving Placement under the Constant Delay Model (KS, WK, IN, LPPPvG), pp. 677–682.
DATE-2002-TienTC: Crosstalk Alleviation for Dynamic PLAs (TKT, TKT, SCC), pp. 683–687.
DATE-2002-LuZKC: Flip-Flop and Repeater Insertion for Early Interconnect Planning (RL, GZ, CKK, KYC), pp. 690–695.
DATE-2002-WongSY #design #estimation: Congestion Estimation with Buffer Planning in Floorplan Design (WCW, CWS, EFYY), pp. 696–701.
DATE-2002-HuangLWG #constraints: Maze Routing with Buffer Insertion under Transition Time Constraints (LDH, ML, DFW, YG), pp. 702–707.
DATE-2002-DingM #performance: Optimal Transistor Tapering for High-Speed CMOS Circuits (LD, PM), pp. 708–713.
DATE-2002-VenerisLAA #fault #incremental #multi: Incremental Diagnosis and Correction of Multiple Faults and Errors (AGV, JBL, MA, MSA), pp. 716–721.
DATE-2002-PomeranzR #fault #multi #set #using: Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults (IP, SMR), pp. 722–729.
DATE-2002-VedulaA #analysis #functional #generative #named #testing: FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis (VMV, JAA), pp. 730–734.
DATE-2002-DoucetSGO #co-evolution #component #composition #design #performance: An Environment for Dynamic Component Composition for Efficient Co-Design (FD, SKS, RKG, MO), pp. 736–743.
DATE-2002-FerrandiRS #constraints #functional #theorem proving #using #verification: Functional Verification for SystemC Descriptions Using Constraint Solving (FF, MR, DS), pp. 744–751.
DATE-2002-EdwardsG #embedded #modelling #using: The Modelling of Embedded Systems Using HASoC (MDE, PNG), pp. 752–759.
DATE-2002-DoboliV #co-evolution #design #functional #specification: A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems (AD, RV), pp. 760–767.
DATE-2002-Selic #realtime #standard #uml: The Real-Time UML Standard: Definition and Application (BS), pp. 770–772.
DATE-2002-Martin02a #design #embedded #motivation #overview #perspective #specification #uml: UML for Embedded Systems Specification and Design: Motivation and Overview (GM), pp. 773–775.
DATE-2002-Jong #design #embedded #realtime #uml: A UML-Based Design Methodology for Real-Time and Embedded Sytems (GGdJ), pp. 776–779.
DATE-2002-QuanH #energy #scheduling: Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor (GQ, XH), pp. 782–787.
DATE-2002-KimKM #algorithm #analysis #realtime #scalability #using: A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time Analysis (WK, JK, SLM), pp. 788–794.
DATE-2002-LogothetisS #generative #modelling #realtime: Extending Synchronous Languages for Generating Abstract Real-Time Models (GL, KS), pp. 795–802.
DATE-2002-GorenZGGLASW #approach #design: An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach (DG, MZ, TCG, RG, BL, AA, AS, IAW), pp. 804–811.
DATE-2002-ChenM #design #metric #physics: Closed-Form Crosstalk Noise Metrics for Physical Design Applications (LHC, MMS), pp. 812–819.
DATE-2002-XuM #matrix: Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects (QX, PM), pp. 820–825.
DATE-2002-Sheehan #library: Library Compatible Ceff for Gate-Level Timing (BNS), pp. 826–830.
DATE-2002-MetraSRF #online #power management #self #testing: Self-Checking Scheme for the On-Line Testing of Power Supply Noise (CM, LS, BR, MF), pp. 832–836.
DATE-2002-Leveugle #automation #detection #fault: Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance (RL), pp. 837–841.
DATE-2002-WuK #algorithm: Exploiting Idle Cycles for Algorithm Level Re-Computing (KW, RK), pp. 842–846.
DATE-2002-BerrojoGCRSEL #injection: New Techniques for Speeding-Up Fault-Injection Campaigns (LB, IG, FC, MSR, GS, LE, CL), pp. 847–852.
DATE-2002-HaubeltTRE #design #flexibility: System Design for Flexibility (CH, JT, KR, RE), pp. 854–861.
DATE-2002-NayakHCB: Accurate Area and Delay Estimators for FPGAs (AN, MH, ANC, PB), pp. 862–869.
DATE-2002-BuchenriederPS #concept #design: A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering (KB, AP, AS), pp. 870–874.
DATE-2002-SavoiuSG #automation #concurrent #modelling #performance #simulation: Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation (NS, SKS, RKG), pp. 875–881.
DATE-2002-SommerRHGMMECSN #design #layout #specification #top-down: From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications (RS, IRH, EH, UG, PM, FM, KE, CC, PS, GN), pp. 884–891.
DATE-2002-GrunDN #memory management: Memory System Connectivity Exploration (PG, NDD, AN), pp. 894–901.
DATE-2002-HettiaratchiCC #generative #memory management #trade-off: Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory (SH, PYKC, TJWC), pp. 902–908.
DATE-2002-MolinaMH #independence #multi: Multiple-Precision Circuits Allocation Independent of Data-Objects Length (MCM, JMM, RH), pp. 909–913.
DATE-2002-GadN #linear #performance #reduction: Efficient Model Reduction of Linear Time-Varying Systems via Compressed Transient System Function (EG, MSN), pp. 916–922.
DATE-2002-CoelhoSP #algorithm #approximate #using: Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation (CPC, LMS, JRP), pp. 923–930.
DATE-2002-ChenBKR #reduction #using: Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods (YC, VB, CKK, KR), pp. 931–935.
DATE-2002-BensoCNP #algorithm #automation #generative #testing: An Optimal Algorithm for the Automatic Generation of March Tests (AB, SDC, GDN, PP), pp. 938–943.
DATE-2002-GoorAC #fault: Minimal Test for Coupling Faults in Word-Oriented Memories (AJvdG, MSA, AC), pp. 944–948.
DATE-2002-Hsiao #fault #identification: Maximizing Impossibilities for Untestable Fault Identification (MSH), pp. 949–953.
DATE-2002-Bose #automation #modelling: Automated Modeling of Custom Digital Circuits for Test (SB), pp. 954–961.
DATE-2002-ArrigoniDPLW #scheduling: False Path Elimination in Quasi-Static Scheduling (GA, LD, CP, LL, YW), pp. 964–970.
DATE-2002-BontempiK #data analysis #performance #predict: A Data Analysis Method for Software Performance Prediction (GB, WK), pp. 971–976.
DATE-2002-LiverisZSG #performance #program transformation: A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications (NDL, NDZ, DS, CEG), pp. 977–983.
DATE-2002-Kandemir #approach #reuse: A Compiler-Based Approach for Improving Intra-Iteration Data Reuse (MTK), pp. 984–990.
DATE-2002-Borel: European CAD from the 60’s to the New Millenium (JB), p. 992.
DATE-2002-GuccioneVB #configuration management #design #platform: Design Technology for Networked Reconfigurable FPGA Platforms (SG, DV, IB), pp. 994–997.
DATE-2002-OzdagBSN #performance #pipes and filters: High-Speed Non-Linear Asynchronous Pipelines (ROO, PAB, MS, SMN), pp. 1000–1007.
DATE-2002-FerrettiB #encoding #pipes and filters #using: Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding (MF, PAB), pp. 1008–1015.
DATE-2002-ChenS #scheduling #synthesis: Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis (CC, MS), pp. 1016–1020.
DATE-2002-ZhaoMB #compilation #design #modelling #set #using: Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models (QZ, BM, TB), pp. 1021–1026.
DATE-2002-BrandtnerW #network #power management #simulation: Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network (TB, RW), pp. 1028–1032.
DATE-2002-ThielenV #performance #simulation: Fast Method to Include Parasitic Coupling in Circuit Simulations (BLAVT, GAEV), pp. 1033–1037.
DATE-2002-DingM02a #modelling #using: Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling (LD, PM), pp. 1038–1043.
DATE-2002-StievanoCMCBK #assessment #megamodelling: Macromodeling of Digital I/O Ports for System EMC Assessment (ISS, FGC, IAM, ZC, WDB, GAK), pp. 1044–1048.
DATE-2002-BlasquezHFLBHB #industrial #verification: Formal Verification Techniques: Industrial Status and Perspectives (JB, MvH, AF, JLL, DB, CH, PB), p. 1050.
DATE-2002-PeymandoustSM #algebra #embedded #optimisation #power management #using: Low Power Embedded Software Optimization Using Symbolic Algebra (AP, TS, GDM), pp. 1052–1058.
DATE-2002-LvWHL #adaptation #encoding #taxonomy: An Adaptive Dictionary Encoding Scheme for SOC Data Buses (TL, WW, JH, HL), pp. 1059–1064.
DATE-2002-PetrovO #embedded #performance: Power Efficient Embedded Processor Ip’s through Application-Specific Tag Compression in Data Caches (PP, AO), pp. 1065–1071.
DATE-2002-PalkovicMC #optimisation #trade-off: Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities (MP, MM, FC), pp. 1072–1077.
DATE-2002-HartongHB #approach #model checking: An Approach to Model Checking for Nonlinear Analog Systems (WH, LH, EB), p. 1080.
DATE-2002-PilarskiH #satisfiability: Speeding up SAT for EDA (SP, GH), p. 1081.
DATE-2002-AloulMS #satisfiability #search-based #using: Search-Based SAT Using Zero-Suppressed BDDs (FAA, MNM, KAS), p. 1082.
DATE-2002-MartinezAQSK #encoding #implementation #power management: An Encoding Technique for Low Power CMOS Implementations of Controllers (MM, MJA, JMQ, HS, MK), p. 1083.
DATE-2002-Dubrova #composition #order: Composition Trees in Finding Best Variable Orderings for ROBDDs (ED), p. 1084.
DATE-2002-AbkeB #automaton #implementation: A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs (JA, EB), p. 1085.
DATE-2002-RezvaniP #concurrent #logic: Concurrent and Selective Logic Extraction with Timing Consideration (PR, MP), p. 1086.
DATE-2002-Kania #approach #multi #using: Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions (DK), p. 1087.
DATE-2002-BerkelaarE #effectiveness #performance: Efficient and Effective Redundancy Removal for Million-Gate Circuits (MRCMB, KvE), p. 1088.
DATE-2002-BystrovKY #design #modelling #partial order #visualisation: Visualization of Partial Order Models in VLSI Design Flow (AVB, MK, AY), p. 1089.
DATE-2002-RigaudFRQ #communication #design #modelling: High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems (JBR, LF, MR, JQ), p. 1090.
DATE-2002-HuVKI #power management: Power-Efficient Trace Caches (JSH, NV, MTK, MJI), p. 1091.
DATE-2002-KandemirK #energy: Reducing Cache Access Energy in Array-Intensive Application (MTK, IK), p. 1092.
DATE-2002-NitschK #embedded #runtime #using: The Use of Runtime Configuration Capabilities for Networked Embedded Systems (CN, UK), p. 1093.
DATE-2002-SkliarovaF #configuration management #hardware #satisfiability #using: A SAT Solver Using Software and Reconfigurable Hardware (IS, AdBF), p. 1094.
DATE-2002-MunzenbergerDSH #design #embedded #realtime #specification #synthesis #validation: A New Time Model for the Specification, Design, Validation and Synthesis of Embedded Real-Time Systems (RM, MD, FS, RH), p. 1095.
DATE-2002-GrajcarG #constraints #multi #scheduling: Improved Constraints for Multiprocessor System Scheduling (MG, WG), p. 1096.
DATE-2002-PenalbaMH #reuse: Maximizing Conditonal Reuse by Pre-Synthesis Transformations (OP, JMM, RH), p. 1097.
DATE-2002-TugsinavisutB #pipes and filters: Control Circuit Templates for Asynchronous Bundled-Data Pipelines (ST, PAB), p. 1098.
DATE-2002-PeyranZ #slicing: Transforming Arbitrary Structures into Topologically Equivalent Slicing Structures (OP, WZ), p. 1099.
DATE-2002-LeeLFCH #problem: A New Formulation for SOC Floorplan Area Minimization Problem (CHL, YCL, WYF, CCC, TMH), p. 1100.
DATE-2002-ChuY #design: Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design (CCNC, EFYY), p. 1101.
DATE-2002-AghaghiriPF #encoding #multi #power management: EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses (YA, MP, FF), p. 1102.
DATE-2002-OrtizKG #estimation #power management: Estimation of Power Consumption in Encoded Data Buses (AGO, LDK, MG), p. 1103.
DATE-2002-Hieu #analysis #design #feedback #linear #optimisation: Optimization Techniques for Design of General and Feedback Linear Analog Amplifier with Symbolic Analysis (TcH), p. 1104.
DATE-2002-LuchettaMP #comparison #fault: Critical Comparison among Some Analog Fault Diagnosis Procedures Based on Symbolic Techniques (AL, SM, MCP), p. 1105.
DATE-2002-StanP: The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits (MRS, AP), p. 1106.
DATE-2002-CathelinSBLC: Substrate Parasitic Extraction for RF Integrated Circuits (AC, DS, DB, YL, FC), p. 1107.
DATE-2002-DuarteVI #power management: A Complete Phase-Locked Loop Power Consumption Model (DD, NV, MJI), p. 1108.
DATE-2002-AbabeiB #clustering #statistics: Statistical Timing Driven Partitioning for VLSI Circuits (CA, KB), p. 1109.
DATE-2002-FranckenVMG #named #simulation: DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators (KF, MV, EM, GGEG), p. 1110.
DATE-2002-HassibiH #automation #design: Automated Optimal Design of Switched-Capacitor Filters (AH, MdMH), p. 1111.
DATE-2002-LinBP #3d #modelling #question: On-Chip Inductance Models: 3D or Not 3D? (TL, MWB, LTP), p. 1112.
DATE-2002-YmeriNMRSV #approach #parametricity #performance: Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate (HY, BN, KM, DDR, MS, SV), p. 1113.
DATE-2002-KhazakaN #megamodelling: Compact Macromodel for Lossy Coupled Transmission Lines (RK, MSN), p. 1114.
DATE-2002-LevantR #design: An EMC-Compliant Design Method of High-Density Integrated Circuits (JLL, MR), p. 1115.
DATE-2002-PomeranzRR #debugging #fault: Finding a Common Fault Response for Diagnosis during Silicon Debug (IP, JR, SMR), p. 1116.
DATE-2002-KumarMB #embedded #testing: IDDT Testing of Embedded CMOS SRAMs (SAK, RZM, DMB), p. 1117.
DATE-2002-BhuniaR #analysis #detection #fault #using: Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis (SB, KR), p. 1118.
DATE-2002-LinLC #feedback #performance: An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits (JWL, CLL, JEC), p. 1119.
DATE-2002-BeroulleBLN #on the #using: On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems (VB, YB, LL, PN), p. 1120.
DATE-2002-KapurWM #logic: Directed-Binary Search in Logic BIST Diagnostics (RK, TWW, MRM), p. 1121.
DATE-2002-FavalliD #approach #design #generative #pseudo #random testing: An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators (MF, MD), p. 1122.
DATE-2002-PomeranzZ #fault #testing #using: Fault Isolation Using Tests for Non-Isolated Blocks (IP, YZ), p. 1123.
DATE-2002-FlottesPR #heuristic #scheduling: A Heuristic for Test Scheduling at System Level (MLF, JP, BR), p. 1124.
DATE-2002-KoranneC #network #problem #scheduling: Formulation of SOC Test Scheduling as a Network Transportation Problem (SK, VSC), p. 1125.
DATE-2002-GericotaASF #concurrent #configuration management #novel: A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs (MGG, GRA, MLS, JMF), p. 1126.
DATE-2002-DrozdLD #array #float #online #performance #testing: Efficient On-Line Testing Method for a Floating-Point Iterative Array Divider (AVD, MVL, JVD), p. 1127.
DATE-2002-BonaSSZSZ #embedded #estimation #optimisation: An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores (AB, MS, DS, VZ, CS, RZ), p. 1128.
DATE-2002-SauerEKJ #design #network: The Fraunhofer Knowledge Network (FKN) for Training in Critical Design Disciplines (AS, GE, LK, WJ), p. 1129.
DATE-2002-IndrusiakGR #analysis #comparative #design #distributed #framework #repository: Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments (LSI, MG, RAdLR), p. 1130.
DATE-2002-StohrSG #named #reuse #using #verification: FlexBench: Reuse of Verification IP to Increase Productivity (BS, MS, JG), p. 1131.
DATE-2002-SoininenKQ #algorithm #architecture #estimation: Mappability Estimation of Architecture and Algorithm (JPS, JK, YQ), p. 1132.
DATE-2002-WilsonRZBK #behaviour #fault #modelling #using: Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS (PRW, JNR, MZ, ADB, YK), p. 1133.
DATE-2002-Hering #parallel #simulation: A Parallel LCC Simulation System (KH), p. 1134.
DATE-2002-BruschiCFS #design #fault #simulation: Error Simulation Based on the SystemC Design Description Language (FB, MC, FF, DS), p. 1135.
DATE-2002-BjorklundL #kernel #towards: Towards a Kernel Language for Heterogeneous Computing (DB, JL), p. 1136.
DATE-2002-CaiGKO #design #top-down #using: Top-Down System Level Design Methodology Using SpecC, VCC and SystemC (LC, DG, PK, MO), p. 1137.
DATE-2002-PozziVI #automation #embedded #identification: Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors (LP, MV, PI), p. 1138.
DATE-2002-BrachtendorfLLMF #continuation #using: Steady State Calculation of Oscillators Using Continuation Methods (HGB, SL, RL, RCM, PF), p. 1139.

Proceedings of the Seventh Conference on Design, Automation and Test in EuropeDATE, 2002.

Contents (228 items)

Proceedings of the Seventh Conference on Design, Automation and Test in Europe
DATE, 2002.