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Travelled to:
1 × USA
Collaborated with:
F.Dartu N.Menezes L.T.Pillage
Talks about:
circuit (1) speed (1) model (1) delay (1) high (1) gate (1) cmos (1)

Person: Jessica Qian

DBLP DBLP: Qian:Jessica

Contributed to:

DAC 19941994

Wrote 1 papers:

DAC-1994-DartuMQP #performance
A Gate-Delay Model for high-Speed CMOS Circuits (FD, NM, JQ, LTP), pp. 576–580.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.