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Collaborated with:
W.D.0006 L.Yin W.Liu H.Yu Z.Chen Y.Zhang
Talks about:
constraint (1) properti (1) executor (1) abstract (1) schedul (1) regular (1) symbol (1) memori (1) refin (1) model (1)

Person: Ji Wang 0001

DBLP DBLP: 0001:Ji_Wang

Contributed to:

ESEC/FSE 20172017
ASE 20182018

Wrote 2 papers:

ESEC-FSE-2017-YuCZWD #java #named
RGSE: a regular property guided symbolic executor for Java (HY, ZC, YZ, JW0, WD0), pp. 954–958.
ASE-2018-Yin0LW #abstraction #constraints #memory management #modelling #refinement #scheduling
Scheduling constraint based abstraction refinement for weak memory models (LY, WD0, WL, JW0), pp. 645–655.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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