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Travelled to:
1 × France
Collaborated with:
S.Turgis J.M.Daga D.Auvergne
Talks about:
invert (1) intern (1) power (1) model (1) minim (1) cmos (1)

Person: Josep M. Portal

DBLP DBLP: Portal:Josep_M=

Contributed to:

ED&TC 19971997

Wrote 1 papers:

EDTC-1997-TurgisDPA #modelling
Internal power modelling and minimization in CMOS inverters (ST, JMD, JMP, DA), pp. 603–608.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.