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Travelled to:
1 × Germany
3 × France
Collaborated with:
J.M.Daga E.Ottaviano S.Turgis J.M.Portal A.Verle X.Michel N.Azémard P.Maurine W.Rahajandraibe C.Dufaza B.Cialdella B.Majoux V.Chowdhury
Talks about:
low (3) voltag (2) applic (2) power (2) cmos (2) temperatur (1) structur (1) protocol (1) determin (1) paramet (1)

Person: Daniel Auvergne

DBLP DBLP: Auvergne:Daniel

Contributed to:

DATE 20052005
DATE 20022002
DATE 19981998
ED&TC 19971997

Wrote 4 papers:

DATE-2005-VerleMAMA #optimisation #power management #protocol
Low Power Oriented CMOS Circuit Optimization Protocol (AV, XM, NA, PM, DA), pp. 640–645.
DATE-2002-RahajandraibeDACMC #parametricity
Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications (WR, CD, DA, BC, BM, VC), pp. 316–321.
Temperature Effect on Delay for Low Voltage Applications (JMD, EO, DA), pp. 680–685.
EDTC-1997-TurgisDPA #modelling
Internal power modelling and minimization in CMOS inverters (ST, JMD, JMP, DA), pp. 603–608.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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