BibSLEIGH corpus
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Travelled to:
3 × France
Collaborated with:
D.Auvergne E.Ottaviano B.Godard L.Torres G.Sassatelli S.Turgis J.M.Portal
Talks about:
temperatur (1) techniqu (1) reliabl (1) voltag (1) memori (1) invert (1) intern (1) effect (1) design (1) applic (1)

Person: Jean Michel Daga

DBLP DBLP: Daga:Jean_Michel

Contributed to:

DATE 20072007
DATE 19981998
ED&TC 19971997

Wrote 3 papers:

DATE-2007-GodardDTS #design #embedded #evaluation #reliability
Evaluation of design for reliability techniques in embedded flash memories (BG, JMD, LT, GS), pp. 1593–1598.
Temperature Effect on Delay for Low Voltage Applications (JMD, EO, DA), pp. 680–685.
EDTC-1997-TurgisDPA #modelling
Internal power modelling and minimization in CMOS inverters (ST, JMD, JMP, DA), pp. 603–608.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.