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Travelled to:
1 × USA
Collaborated with:
T.Bergstraesser K.Hafner S.Wallstab
Talks about:
architectur (1) processor (1) synthesi (1) method (1) smart (1) vlsi (1) tool (1) chip (1)

Person: Jürgen Gessner

DBLP DBLP: Gessner:J=uuml=rgen

Contributed to:

DAC 19881988

Wrote 1 papers:

DAC-1988-BergstraesserGHW #architecture #named #synthesis #tool support
SMART: Tools and Methods for Synthesis of VLSI Chips with Processor Architecture (TB, JG, KH, SW), pp. 654–657.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.