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Travelled to:
1 × France
Collaborated with:
J.Fan W.Feng
Talks about:
waveform (1) current (1) circuit (1) domain (1) simul (1) accur (1) vlsi (1) time (1)

Person: Jyh-Herng Wang

DBLP DBLP: Wang:Jyh=Herng

Contributed to:

EDAC-ETC-EUROASIC 19941994

Wrote 1 papers:

EDAC-1994-WangFF
An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits (JHW, JTF, WSF), pp. 562–566.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.