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Travelled to:
1 × Germany
2 × France
Collaborated with:
W.Dehaene F.Catthoor H.Wang M.Miranda H.Ymeri B.Nauwelaers D.D.Roest M.Stucchi S.Vandenberghe G.G.E.Gielen P.Christie D.Draxelmayr E.Janssens T.Vucurevich A.Cuomo G.Martin P.Groeneveld R.Lauwereins P.v.d.Steeg R.Wilson
Talks about:
interconnect (2) design (2) semiconduct (1) technolog (1) submicron (1) systemat (1) substrat (1) approach (1) variabl (1) process (1)

Person: Karen Maex

DBLP DBLP: Maex:Karen

Contributed to:

DATE 20052005
DATE v1 20042004
DATE 20022002

Wrote 4 papers:

DATE-2005-GielenDCDJMV #design #question
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? (GGEG, WD, PC, DD, EJ, KM, TV), pp. 36–42.
DATE-2005-WangMDCM #analysis #embedded #energy #process #variability
Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules (HW, MM, WD, FC, KM), pp. 914–919.
DATE-v1-2004-CatthoorCMGLMSW #design #how #problem #question #scalability
How Can System-Level Design Solve the Interconnect Technology Scaling Problem? (FC, AC, GM, PG, RL, KM, PvdS, RW), pp. 332–339.
DATE-2002-YmeriNMRSV #approach #parametricity #performance
Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate (HY, BN, KM, DDR, MS, SV), p. 1113.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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