BibSLEIGH — Georges_G_E

Travelled to:

14 × USA
8 × Germany
9 × France

Collaborated with:

W.M.C.Sansen E.Maricau E.Martens T.McConaghy M.Steyaert T.Eeckelaert W.Daems P.Vanassche S.Donnay M.Vogels B.Liu E.Lauwers J.Vandenbussche D.d.Jonghe H.D.Man W.Verhaegen G.V.d.Plas P.Wambacq J.Craninckx M.Badaroglu P.Palmers T.Kiely B.D.Smedt W.Eberle P.H.N.D.Wit R.Schoofs K.Uyttenhove C.D.Ranter P.J.Vancorenland J.V.Rethy W.Dehaene J.Messaoudi A.Xhakoni D.S.S.Bello F.V.Fernández Y.Ke O.Bajdechi J.H.Huijsing W.Kruiskamp D.Leenaerts K.Lampaert G.Vandersteen D.Deschrijver T.Dhaene P.Gao X.Xing Y.He P.Reynaert D.Binkley H.E.Graeb J.S.Roychowdhury K.Francken L.R.Carley R.A.Rutenbar H.Danneels V.D.Smedt H.Aliakbarian S.Radiom G.A.E.Vandenbosch B.Sorensen H.Casier P.Magarshack J.Rodriguez F.Leyn B.Tasic H.D.Stratigopoulos C.M.Lopez S.Musa C.Bartic R.Puers M.Ranjan A.Agarwal H.Sampath R.Vemuri A.v.d.Bosch W.v.Bokhoven K.Swings M.M.Shulaker G.Hills H.Chen H.P.Wong S.Mitra P.Christie D.Draxelmayr E.Janssens K.Maex T.Vucurevich K.Tiri I.Verbauwhede B.D.Muer G.Ying A.Kuehlmann K.S.Kundert E.Grimme M.O'Leary S.Tare W.Wong A.S.Mecheri T.K.T.Nguyen R.Campagnolo A.Burdett C.Toumazou B.Volckaerts P.Dobrovolný M.v.Heijningen V.Gravot M.Engels I.Bolsens J.Loeckx J.Martín-Martínez B.Kaczer G.Groeseneken R.Rodríguez M.Nafría

Talks about:

analog (30) circuit (26) design (19) model (18) integr (11) use (10) perform (9) signal (9) simul (9) optim (9)

Person: Georges G. E. Gielen

DBLP: Gielen:Georges_G=_E=

Facilitated 2 volumes:

Contributed to:

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

2000

1999

1998

1997

1996

1995

1994

Wrote 68 papers:

DAC-2013-ShulakerRHCGWM #named: Sacha: the Stanford carbon nanotube controlled handshaking robot (MMS, JVR, GH, HYC, GGEG, HSPW, SM), p. 3.
DATE-2013-GielenM #modelling #probability #simulation: Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS (GGEG, EM), pp. 326–331.
DATE-2013-JongheDDG #modelling #recursion: Extracting analytical nonlinear models from analog circuits by recursive vector fitting of transfer function trajectories (DdJ, DD, TD, GGEG), pp. 1448–1453.
DATE-2013-RethyDSDG #interface #network #power management: A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks (JVR, HD, VDS, WD, GGEG), pp. 1431–1435.
DAC-2012-LiuARVG #component #multi #performance #synthesis: Efficient multi-objective synthesis for microwave components based on computational intelligence techniques (BL, HA, SR, GAEV, GGEG), pp. 542–548.
DATE-2012-GaoXCG #design: Design of an intrinsically-linear double-VCO-based ADC with 2nd-order noise shaping (PG, XX, JC, GGEG), pp. 1215–1220.
DATE-2012-JongheMGMTS #modelling #roadmap #testing #verification: Advances in variation-aware modeling, verification, and testing of analog ICs (DdJ, EM, GGEG, TM, BT, HGDS), pp. 1615–1620.
DATE-2012-LiuMG #estimation #performance #problem: A fast analog circuit yield estimation method for medium and high dimensional problems (BL, JM, GGEG), pp. 751–756.
DATE-2012-MaricauJG #analysis #learning #multi #reliability #using: Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection (EM, DdJ, GGEG), pp. 745–750.
DATE-2012-XhakoniBG #3d #image #performance: Impact of TSV area on the dynamic range and frame rate performance of 3D-integrated image sensors (AX, DSSB, GGEG), pp. 836–839.
DATE-2011-GielenMW #analysis #reliability: Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation (GGEG, EM, PHNDW), pp. 1474–1479.
DATE-2011-LiuHRG #optimisation #process #using: Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate model (BL, YH, PR, GGEG), pp. 1101–1106.
DATE-2011-LopezMBPGE #design #interface #process #programmable: Systematic design of a programmable low-noise CMOS neural interface for cell activity recording (CML, SM, CB, RP, GGEG, WE), pp. 818–823.
DATE-2011-MaricauG #analysis #probability #reliability: Stochastic circuit reliability analysis (EM, GGEG), pp. 1285–1290.
DATE-2010-LiuFG #optimisation #performance: An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique (BL, FVF, GGEG), pp. 1106–1111.
DATE-2010-MaricauG #complexity #reliability #simulation #variability: Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity (EM, GGEG), pp. 1094–1099.
DAC-2009-YingKKGGOTW #how #question: Guess, solder, measure, repeat: how do I get my mixed-signal chip right? (GY, AK, KSK, GGEG, EG, MO, ST, WW), pp. 520–521.
DATE-2009-EberleMNGCBTV #challenge: Health-care electronics The market, the challenges, the progress (WE, ASM, TKTN, GGEG, RC, AB, CT, BV), pp. 1030–1034.
DATE-2009-KeCG #configuration management #design: A design methodology for fully reconfigurable Delta-Sigma data converters (YK, JC, GGEG), pp. 1379–1384.
DATE-2009-MaricauG #performance #reliability #simulation #variability: Efficient reliability simulation of analog ICs including variability and time-varying stress (EM, GGEG), pp. 1238–1241.
DATE-2009-PalmersMSG #multi: Massively multi-topology sizing of analog integrated circuits (PP, TM, MS, GGEG), pp. 706–711.
DATE-2008-BinkleyGGR #design: From Transistor to PLL — Analogue Design and EDA Methods (DB, HEG, GGEG, JSR).
DATE-2008-GielenWMLMKGRN #challenge #reliability: Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies (GGEG, PHNDW, EM, JL, JMM, BK, GG, RR, MN), pp. 1322–1327.
DAC-2007-McConaghyPGS #multi: Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies (TM, PP, GGEG, MS), pp. 944–947.
DATE-2007-EeckelaertSGSS #performance #synthesis: An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection (TE, RS, GGEG, MS, WMCS), pp. 81–86.
DAC-2006-EeckelaertSGSS #design #optimisation #standard: Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard (TE, RS, GGEG, MS, WMCS), pp. 25–30.
DATE-2006-MartensE #synthesis #top-down: Top-down heterogeneous synthesis of analog and mixed-signal systems (EM, GGEG), pp. 275–280.
DATE-2006-McConaghyG #canonical #modelling #performance: Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns (TM, GGEG), pp. 269–274.
DAC-2005-GielenME #modelling #performance #synthesis: Performance space modeling for hierarchical synthesis of analog integrated circuits (GGEG, TM, TE), pp. 881–886.
DATE-2005-EeckelaertMG #multi #performance #synthesis #using: Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces (TE, TM, GGEG), pp. 1070–1075.
DATE-2005-GielenDCDJMV #design #question: Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? (GGEG, WD, PC, DD, EJ, KM, TV), pp. 36–42.
DATE-2005-MartensG #integration #orthogonal #polynomial #simulation #using: Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series (EM, GGEG), pp. 120–125.
DATE-2005-McConaghyEG #canonical #generative #named #programming #search-based: CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming (TM, TE, GGEG), pp. 1082–1087.
DAC-2004-PlasBVDWDGM #simulation: High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects (GVdP, MB, GV, PD, PW, SD, GGEG, HDM), pp. 854–859.
DATE-v1-2004-BadarogluWPDGM #reduction: Digital Ground Bounce Reduction by Phase Modulation of the Clock (MB, PW, GVdP, SD, GGEG, HDM), pp. 88–93.
DATE-v1-2004-KielyG #modelling #performance #using: Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines (TK, GGEG), pp. 448–453.
DATE-v1-2004-MartensG #architecture #design: A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design (EM, GGEG), pp. 436–441.
DATE-v1-2004-RanjanVASVG #modelling #performance #synthesis #using: Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models (MR, WV, AA, HS, RV, GGEG), pp. 604–609.
DAC-2003-VogelsG #architecture: Architectural selection of A/D converters (MV, GGEG), pp. 974–977.
DATE-2003-EberleVWDGM #automation #behaviour #modelling #simulation: Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver (WE, GV, PW, SD, GGEG, HDM), pp. 10642–10649.
DATE-2003-EeckelaertDGS #modelling #performance: Generalized Posynomial Performance Modeling (TE, WD, GGEG, WMCS), pp. 10250–10255.
DATE-2003-MartensG: A Model of Computation for Continuous-Time ?-? Modulators (EM, GGEG), pp. 10162–10167.
DATE-2003-SmedtG #bound #design #named: HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits (BDS, GGEG), pp. 10256–10263.
DATE-2003-VanasscheGS #analysis #detection #domain model #modelling: Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors (PV, GGEG, WMCS), pp. 10238–10243.
DATE-2003-VogelsG: Figure of Merit Based Selection of A/D Converters (MV, GGEG), pp. 11090–11091.
DAC-2002-BadarogluTDWMVG #optimisation #reduction #using: Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients (MB, KT, SD, PW, HDM, IV, GGEG), pp. 399–404.
DAC-2002-BajdechiHG #design: Optimal design of delta-sigma ADCs by design space exploration (OB, JHH, GGEG), pp. 443–448.
DAC-2002-DaemsGS #modelling #performance: An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits (WD, GGEG, WMCS), pp. 431–436.
DAC-2002-VanasscheGS #behaviour #modelling: Behavioral modeling of (coupled) harmonic oscillators (PV, GGEG, WMCS), pp. 536–541.
DAC-2002-VandenbusscheULSG #design: Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter (JV, KU, EL, MS, GGEG), pp. 449–454.
DATE-2002-DaemsGS #approach #linear #performance: A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics (WD, GGEG, WMCS), pp. 268–273.
DATE-2002-FranckenVMG #named #simulation: DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators (KF, MV, EM, GGEG), p. 1110.
DATE-2002-VanasscheGS #behaviour #matrix #modelling #using: Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices (PV, GGEG, WMCS), pp. 279–284.
DATE-2002-VandenbusscheLUSG #design: Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter (JV, EL, KU, MS, GGEG), pp. 357–361.
DAC-2001-VerhaegenG #analysis #linear #performance #scalability: Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits (WV, GGEG), pp. 139–144.
DATE-2001-BadarogluHGDMGEB #generative #multi #scalability #simulation: High-level simulation of substrate noise generation from large digital circuits with multiple supplies (MB, MvH, VG, SD, HDM, GGEG, ME, IB), pp. 326–330.
DATE-2001-GielenSCMR #challenge #design: Design challenges and emerging EDA solutions in mixed-signal IC design (GGEG, BS, HC, PM, JR), pp. 694–695.
DATE-2001-VanasscheGS #exponential #performance #simulation #using: Efficient time-domain simulation of telecom frontends using a complex damped exponential signal model (PV, GGEG, WMCS), pp. 169–175.
DAC-2000-PlasVDBGS #design: Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter (GVdP, JV, WD, AvdB, GGEG, WMCS), pp. 452–457.
DAC-2000-RanterMPVSGS #automation #design #layout #named: CYCLONE: automated design and layout of RF LC-oscillators (CDR, BDM, GVdP, PJV, MS, GGEG, WMCS), pp. 11–14.
DAC-2000-VancorenlandRSG #algorithm #design #using: Optimal RF design using smart evolutionary algorithms (PJV, CDR, MS, GGEG), pp. 7–10.
DAC-1999-DaemsGS #analysis #complexity #reduction: Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits (WD, GGEG, WMCS), pp. 958–963.
DATE-1999-LauwersG #estimation #performance: A Power Estimation Model for High-Speed CMOS A/D Converters (EL, GGEG), pp. 401–405.
DATE-1998-VandenbusscheDLGS #design #interface #specification #top-down: Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon (JV, SD, FL, GGEG, WMCS), pp. 716–720.
EDTC-1997-DonnayGSKLB #interface #synthesis: High-level synthesis of analog sensor interface front-ends (SD, GGEG, WMCS, WK, DL, WvB), pp. 56–60.
DAC-1996-CarleyGRS #synthesis #tool support: Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies (LRC, GGEG, RAR, WMCS), pp. 298–303.
DAC-1995-LampaertGS: Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits (KL, GGEG, WMCS), pp. 445–449.
EDAC-1994-DonnaySGSKL #automation #design: A Methodology for Analog Design Automation in Mixed-Signal ASICs (SD, KS, GGEG, WMCS, WK, DL), pp. 530–534.