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Travelled to:
2 × USA
Collaborated with:
D.Blaauw J.Wang V.Zolotov M.Zhao R.Panda B.Young
Talks about:
analysi (2) induct (2) design (1) model (1) issu (1) chip (1)

Person: Kaushik Gala

DBLP DBLP: Gala:Kaushik

Contributed to:

DAC 20012001
DAC 20002000

Wrote 2 papers:

DAC-2001-GalaBWZZ #analysis #design
Inductance 101: Analysis and Design Issues (KG, DB, JW, VZ, MZ), pp. 329–334.
DAC-2000-GalaZPYWB #analysis #modelling
On-chip inductance modeling and analysis (KG, VZ, RP, BY, JW, DB), pp. 63–68.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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