BibSLEIGH — Proceedings of the 37th Design Automation Conference

Giovanni De Micheli
Proceedings of the 37th Design Automation Conference
DAC, 2000.

SYS

@proceedings{DAC-2000,
	acmid         = "337292",
	address       = "Los Angeles, California, USA",
	editor        = "Giovanni De Micheli",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 37th Design Automation Conference}",
	year          = 2000,
}

Contents (149 items)

DAC-2000-PhelpsKRCH #case study #synthesis: A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC (RP, MK, RAR, LRC, JRH), pp. 1–6.
DAC-2000-VancorenlandRSG #algorithm #design #using: Optimal RF design using smart evolutionary algorithms (PJV, CDR, MS, GGEG), pp. 7–10.
DAC-2000-RanterMPVSGS #automation #design #layout #named: CYCLONE: automated design and layout of RF LC-oscillators (CDR, BDM, GVdP, PJV, MS, GGEG, WMCS), pp. 11–14.
DAC-2000-GaurdianiSMSC #bound #component #constant #simulation #statistics: An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects (CG, SS, PM, PS, DC), pp. 15–18.
DAC-2000-PiS #analysis #approach #diagrams #multi: Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits (TP, CJRS), pp. 19–22.
DAC-2000-MoonKRS #image: To split or to conjoin: the question in image computation (IHM, JHK, KR, FS), pp. 23–28.
DAC-2000-BloemRS #model checking: Symbolic guided search for CTL model checking (RB, KR, FS), pp. 29–34.
DAC-2000-YangT #lazy evaluation #model checking: Lazy symbolic model checking (JY, AT), pp. 35–38.
DAC-2000-HettSB #distance #finite #state machine #traversal: Distance driven finite state machine traversal (AH, CS, BB), pp. 39–42.
DAC-2000-GhoshF #automation #diagrams #functional #generative #using: Automatic test pattern generation for functional RTL circuits using assignment decision diagrams (IG, MF), pp. 43–48.
DAC-2000-HarrisT #architecture #clustering #testing: Interconnect testing in cluster-based FPGA architectures (IGH, RT), pp. 49–54.
DAC-2000-BayraktarogluO #fault: Improved fault diagnosis in scan-based BIST via superposition (IB, AO), pp. 55–58.
DAC-2000-PomeranzR #fault #on the: On diagnosis of pattern-dependent delay faults (IP, SMR), pp. 59–62.
DAC-2000-GalaZPYWB #analysis #modelling: On-chip inductance modeling and analysis (KG, VZ, RP, BY, JW, DB), pp. 63–68.
DAC-2000-YouVMX #approach #design #multi: A practical approach to parasitic extraction for design of multimillion-transistor integrated circuits (EY, LV, JM, WX), pp. 69–74.
DAC-2000-LevySMW #analysis #performance: A rank-one update method for efficient processing of interconnect parasitics in timing analysis (HL, WS, DM, JW), pp. 75–78.
DAC-2000-KahngMS #analysis #on the: On switch factor based analysis of coupled RC interconnects (ABK, SM, ES), pp. 79–84.
DAC-2000-JongeneelWBO: Area and search space control for technology mapping (DJJ, YW, RKB, RHJMO), pp. 86–91.
DAC-2000-YangCS #logic #named #optimisation: BDS: a BDD-based logic optimization system (CY, MJC, VS), pp. 92–97.
DAC-2000-UmKL #fine-grained #optimisation #power management #synthesis: A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis (JU, TK, CLL), pp. 98–103.
DAC-2000-ZhouW #composition #power management: Optimal low power X OR gate decomposition (HZ, DFW), pp. 104–107.
DAC-2000-MeguerdichianP: Watermarking while preserving the critical path (SM, MP), pp. 108–111.
DAC-2000-VelevB #branch #exception #functional #multi #predict #verification: Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction (MNV, REB), pp. 112–117.
DAC-2000-HuangC #composition #constraints: Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques (CYH, KTC), pp. 118–123.
DAC-2000-WilsonD #reliability #simulation #using #verification: Reliable verification using symbolic simulation with scalar values (CW, DLD), pp. 124–129.
DAC-2000-CurrieHR #automation #verification: Automatic formal verification of DSP software (DWC, AJH, SPR), pp. 130–135.
DAC-2000-ZorianM #design #how #question: System chip test: how will it impact your design? (YZ, EJM), pp. 136–141.
DAC-2000-ChuengDRR #challenge: Test challenges for deep sub-micron technologies (KTC, SD, MR, KR), pp. 142–149.
DAC-2000-ZhaoPSECB #analysis #network: Hierarchical analysis of power distribution networks (MZ, RP, SSS, TE, RC, DB), pp. 150–155.
DAC-2000-NassifK #grid #performance #power management #simulation: Fast power grid simulation (SRN, JNK), pp. 156–161.
DAC-2000-ChaudhryBPE #analysis: Current signature compression for IR-drop analysis (RC, DB, RP, TE), pp. 162–167.
DAC-2000-LiuNPS: Impact of interconnect variations on the clock skew of a gigahertz microprocessor (YL, SRN, LTP, AJS), pp. 168–171.
DAC-2000-MehrotraSBCVN #modelling #performance: A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance (VM, SLS, DSB, AC, RV, SRN), pp. 172–175.
DAC-2000-YangP #multi #performance #simulation: A multi-interval Chebyshev collocation method for efficient high-accuracy RF circuit simulation (BY, JRP), pp. 178–183.
DAC-2000-Phillips #framework #reduction: Projection frameworks for model reduction of weakly nonlinear systems (JRP), pp. 184–189.
DAC-2000-KashyapK: A realizable driving point model for on-chip interconnect with inductance (CVK, BK), pp. 190–195.
DAC-2000-GoelL #verification: Formal verification of an IBM CoreConnect processor local bus arbiter core (AG, WRL), pp. 196–200.
DAC-2000-AagaardJKKS #algorithm #verification: Formal verification of iterative algorithms in microprocessors (MA, RBJ, RK, KRK, CJHS), pp. 201–206.
DAC-2000-LachMP #debugging #detection #fault #locality #performance: Efficient error detection, localization, and correction for FPGA-based debugging (JL, WHMS, MP), pp. 207–212.
DAC-2000-SouriBMS #analysis #design #motivation #multi #performance: Multiple Si layer ICs: motivation, performance analysis, and design implications (SJS, KB, AM, KS), pp. 213–220.
DAC-2000-BorosRP #configuration management #multi: High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system (VEB, ADR, SP), pp. 221–226.
DAC-2000-NiemierKK #design #novel #quantum #tool support: A design of and design tools for a novel quantum dot based microprocessor (MTN, MJK, PMK), pp. 227–232.
DAC-2000-LevyBBDGOOSZ #analysis #design #named: ClariNet: a noise analysis tool for deep submicron design (RL, DB, GB, AD, AG, CO, BO, SS, VZ), pp. 233–238.
DAC-2000-ShepardK #analysis: Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology (KLS, DJK), pp. 239–242.
DAC-2000-SomasekharCRYD #analysis: Dynamic noise analysis in precharge-evaluate circuits (DS, SHC, KR, YY, VD), p. 243.
DAC-2000-WangN #analysis #linear #multi #order: Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources (JMW, TVN), pp. 247–252.
DAC-2000-McDonaldB #clustering #scheduling #simulation #using: Symbolic timing simulation using cluster scheduling (CBM, REB), pp. 254–259.
DAC-2000-Hassoun #analysis #bound #using: Critical path analysis using a dynamically bounded delay model (SH), pp. 260–265.
DAC-2000-ArunachalamRP #analysis #named: TACO: timing analysis with coupling (RA, KR, LTP), pp. 266–269.
DAC-2000-BlaauwPD #graph: Removing user specified false paths from timing graphs (DB, RP, AD), pp. 270–273.
DAC-2000-CongLW #clustering #multi #performance: Performance driven multi-level and multiway partitioning with retiming (JC, SKL, CW), pp. 274–279.
DAC-2000-KimNK #logic #synthesis: Domino logic synthesis minimizing crosstalk (KWK, UN, SMK), pp. 280–285.
DAC-2000-ChangCSM #detection #functional #performance #symmetry #using: Fast post-placement rewiring using easily detectable functional symmetries (CWJC, CKC, PS, MMS), pp. 286–289.
DAC-2000-CongH #array #incremental #programmable: Depth optimal incremental mapping for field programmable gate arrays (JC, HH), pp. 290–293.
DAC-2000-LekatsasHW #design #embedded #power management: Code compression for low power embedded system design (HL, JH, WW), pp. 294–299.
DAC-2000-BeniniMMP #embedded #optimisation #synthesis: Synthesis of application-specific memories for power optimization in embedded systems (LB, AM, EM, MP), pp. 300–303.
DAC-2000-KandemirVIY #compilation #optimisation: Influence of compiler optimizations on system power (MTK, NV, MJI, WY), pp. 304–307.
DAC-2000-GebotysGW #architecture #power management: Power minimization derived from architectural-usage of VLIW processors (CHG, RJG, SW), pp. 308–311.
DAC-2000-DickLRJ #analysis #embedded #operating system: Power analysis of embedded operating systems (RPD, GL, AR, NKJ), pp. 312–315.
DAC-2000-GrunDN #compilation #memory management: Memory aware compilation through accurate timing extraction (PG, NDD, AN), pp. 316–321.
DAC-2000-Edwards #compilation: Compiling Esterel into sequential code (SAE), pp. 322–327.
DAC-2000-OmnesFC #co-evolution #design #embedded #interactive #multi #throughput: Interactive co-design of high throughput embedded multimedia (TJFO, TF, FC), pp. 328–331.
DAC-2000-GhazalNR #performance #predict: Predicting performance potential of modern DSPs (NG, ARN, JMR), pp. 332–335.
DAC-2000-YeVKI #design #energy #estimation #using: The design and use of simplepower: a cycle-accurate energy estimation tool (WY, NV, MTK, MJI), pp. 340–345.
DAC-2000-BrandoleseFSS #energy #estimation: An instruction-level functionally-based energy estimation model for 32-bits microprocessors (CB, WF, FS, DS), pp. 346–351.
DAC-2000-QiuWP #petri net #power management #probability #using: Dynamic power management of complex systems using generalized stochastic Petri nets (QQ, QW, MP), pp. 352–356.
DAC-2000-MacchiaruloM: Wave-steering one-hot encoded FSMs (LM, MMS), pp. 357–360.
DAC-2000-CarloniS #analysis #latency #optimisation #performance: Performance analysis and optimization of latency insensitive systems (LPC, ALSV), pp. 361–367.
DAC-2000-JagannathanHL #algorithm #performance: A fast algorithm for context-aware buffer insertion (AJ, SWH, JL), pp. 368–373.
DAC-2000-LaiW: Maze routing with buffer insertion and wiresizing (ML, DFW), pp. 374–378.
DAC-2000-CongY: Routing tree construction under fixed buffer locations (JC, XY), pp. 379–384.
DAC-2000-AdlerBHB #verification: A current driven routing and verification methodology for analog applications (TA, HB, LH, EB), pp. 385–389.
DAC-2000-PaulPT #hardware #modelling #virtual machine: A codesign virtual machine for hierarchical, balanced hardware/software system modeling (JMP, SNP, DET), pp. 390–395.
DAC-2000-DesmetVM #generative #operating system: Operating system based software generation for systems-on-chip (DD, DV, HDM), pp. 396–401.
DAC-2000-KockSWBKLVE #modelling #named: YAPI: application modeling for signal processing systems (EAdK, WJMS, PvdW, JYB, WMK, PL, KAV, GE), pp. 402–405.
DAC-2000-BrunelKKPPKS #communication: COSY communication IP’s (JYB, WMK, HJHNK, FP, LP, EAdK, WJMS), pp. 406–409.
DAC-2000-ChouB #coordination #distributed #embedded #optimisation #synthesis: Synthesis and optimization of coordination controllers for distributed embedded systems (PHC, GB), pp. 410–415.
DAC-2000-ChiouJRD #embedded #memory management #using: Application-specific memory management for embedded systems using software-controlled caches (DC, PJ, LR, SD), pp. 416–419.
DAC-2000-BergamaschiL #design #using: Designing systems-on-chip using cores (RAB, WRL), pp. 420–425.
DAC-2000-Puig-MedinaEK #configuration management #verification: Verification of configurable processor cores (MPM, GE, PK), pp. 426–431.
DAC-2000-Chakrabarty #architecture #constraints #design: Design of system-on-a-chip test access architectures under place-and-route and power constraints (KC), pp. 432–437.
DAC-2000-VandersteenWRDDEB #data flow #performance #simulation: A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers (GV, PW, YR, PD, SD, ME, IB), pp. 440–445.
DAC-2000-HeijningenBDEB #generative #power management #simulation: High-level simulation of substrate noise generation including power supply noise coupling (MvH, MB, SD, ME, IB), pp. 446–451.
DAC-2000-PlasVDBGS #design: Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter (GVdP, JV, WD, AvdB, GGEG, WMCS), pp. 452–457.
DAC-2000-ChangCWW #representation: B*-Trees: a new representation for non-slicing floorplans (YCC, YWC, GMW, SWW), pp. 458–463.
DAC-2000-PangBLC #constraints #representation #symmetry: Block placement with symmetry constraints based on the O-tree non-slicing representation (YP, FB, KL, CKC), pp. 464–467.
DAC-2000-ChenK #approximate #linear #programming: Floorplan sizing by linear programming approximation (PC, ESK), pp. 468–471.
DAC-2000-OuP #clustering: Timing-driven placement based on partitioning with dynamic cut-net control (SLTO, MP), pp. 472–476.
DAC-2000-CaldwellKM #question #recursion: Can recursive bisection alone produce routable placements? (AEC, ABK, ILM), pp. 477–482.
DAC-2000-NataleSB #constraints #scheduling: Task scheduling with RT constraints (MDN, ALSV, FB), pp. 483–488.
DAC-2000-CortadellaKLMMPWS #embedded #generative #scheduling: Task generation and compile-time scheduling for mixed data-control embedded software (JC, AK, LL, MM, SM, CP, YW, ALSV), pp. 489–494.
DAC-2000-ShinKC #analysis #embedded #multi #performance #realtime: Schedulability-driven performance analysis of multiple mode embedded real-time systems (YS, DK, KC), pp. 495–500.
DAC-2000-BoulisS #configuration management #design #hardware: System design of active basestations based on dynamically reconfigurable hardware (AB, MBS), pp. 501–506.
DAC-2000-LiCDHKS #architecture #co-evolution #configuration management #design #embedded: Hardware-software co-design of embedded reconfigurable architectures (YL, TC, ED, REH, UK, JS), pp. 507–512.
DAC-2000-LahiriRLD #architecture #communication #design: Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips (KL, AR, GL, SD), pp. 513–518.
DAC-2000-YuWK #algorithm #network #order #reduction: Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks (QY, JMW, ESK), pp. 520–525.
DAC-2000-GadDNA #distributed #multi #order #reduction: Passive model order reduction of multiport distributed interconnects (EG, AD, MSN, RA), pp. 526–531.
DAC-2000-Sheehan #predict: Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments (BNS), pp. 532–535.
DAC-2000-Zhao #3d: Singularity-treated quadrature-evaluated method of moments solver for 3-D capacitance extraction (JZ), pp. 536–539.
DAC-2000-WangKS #clustering #latency #memory management #scheduling: Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications (ZW, MK, EHMS), pp. 540–545.
DAC-2000-NarasimhanR #bound #on the #problem #scheduling #synthesis: On lower bounds for scheduling problems in high-level synthesis (MN, JR), pp. 546–551.
DAC-2000-HorstmannshoffM #code generation #data flow #graph #performance: Efficient building block based RTL code generation from synchronous data flow graphs (JH, HM), pp. 552–555.
DAC-2000-EllerveeMCH #data type: System-level data format exploration for dynamically allocated data structures (PE, MM, FC, AH), pp. 556–559.
DAC-2000-FotyB #design #modelling: MOSFET modeling and circuit design: re-establishing a lost connection (DF, DB), p. 560.
DAC-2000-HutchingsN #design #programming language #using: Using general-purpose programming languages for FPGA design (BLH, BEN), pp. 561–566.
DAC-2000-ChangC #architecture #metric: An architecture-driven metric for simultaneous placement and global routing for FPGAs (YWC, YTC), pp. 567–572.
DAC-2000-SinghLFMLKB #case study #configuration management #multi #named: MorphoSys: case study of a reconfigurable computing system targeting multimedia applications (HS, GL, EMCF, RM, MHL, FJK, NB), pp. 573–578.
DAC-2000-KirovskiLWP #forensics #tool support: Forensic engineering techniques for VLSI CAD tools (DK, DTL, JLW, MP), pp. 581–586.
DAC-2000-QuP #constraints #using: Fingerprinting intellectual property using constraint-addition (GQ, MP), pp. 587–592.
DAC-2000-DalpassoBB #hardware: Hardware/software IP protection (MD, AB, LB), pp. 593–596.
DAC-2000-FinF #analysis #simulation: A Web-CAD methodology for IP-core analysis and simulation (AF, FF), pp. 597–600.
DAC-2000-CabodiQS #optimisation #verification: Optimizing sequential verification by retiming transformations (GC, SQ, FS), pp. 601–606.
DAC-2000-HsiehBLS #design #embedded #performance: Efficient methods for embedded system design space exploration (HH, FB, LL, ALSV), pp. 607–612.
DAC-2000-NouraniCP: Synthesis-for-testability of controller-datapath pairs that use gated clocks (MN, JC, CAP), pp. 613–618.
DAC-2000-BaiDR #self: Self-test methodology for at-speed test of crosstalk in chip interconnects (XB, SD, JR), pp. 619–624.
DAC-2000-ChenDSSC #embedded #hardware #self: Embedded hardware and software self-testing methodologies for processor cores (LC, SD, PS, KS, YC), pp. 625–630.
DAC-2000-AttarhaNL #fault #fuzzy #logic #modelling #simulation #using: Modeling and simulation of real defects using fuzzy logic (AA, MN, CL), pp. 631–636.
DAC-2000-ChinneyK #perspective: Closing the gap between ASIC and custom: an ASIC perspective (DGC, KK), pp. 637–642.
DAC-2000-DallyC #design: The role of custom design in ASIC Chips (WJD, AC), pp. 643–647.
DAC-2000-SundararajanSP #named: MINFLOTRANSIT: min-cost flow based transistor sizing tool (VS, SSS, KKP), pp. 649–664.
DAC-2000-KetkarKS #modelling: Convex delay models for transistor sizing (MK, KK, SSS), pp. 655–660.
DAC-2000-NemaniT #design: Macro-driven circuit design methodology for high-performance datapaths (MN, VT), pp. 661–666.
DAC-2000-TianWB #modelling: Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability (RT, DFW, RB), pp. 667–670.
DAC-2000-ChenKRZ #synthesis: Practical iterated fill synthesis for CMP uniformity (YC, ABK, GR, AZ), pp. 671–674.
DAC-2000-SilvaS #automation #design #satisfiability: Boolean satisfiability in electronic design automation (JPMS, KAS), pp. 675–680.
DAC-2000-JainMMWL #analysis #canonical #complexity #composition #graph #how: Analysis of composition complexity and how to obtain smaller canonical graphs (JJ, KM, DM, IW, YL), pp. 681–686.
DAC-2000-LuJCF #performance #using: Efficient variable ordering using aBDD based sampling (YL, JJ, EMC, MF), pp. 687–692.
DAC-2000-CaldwellCKKLMOSS #named: GTX: the MARCO GSRC technology extrapolation system (AEC, YC, ABK, FK, HL, ILM, MO, DS, DS), pp. 693–698.
DAC-2000-HamerLBS #framework #simulation: A system simulation framework (PvdH, WPMvdL, PB, NWS), pp. 699–704.
DAC-2000-FenstermakerGKMT #architecture #design #metric #named #optimisation #process: METRICS: a system architecture for design process optimization (SF, DG, ABK, SM, BT), pp. 705–710.
DAC-2000-CoudertMMS #framework: Web-based frameworks to enable CAD RD (OC, ILM, CM, ES), p. 711.
DAC-2000-PoslusznyABCDFHKKLMNPPSTV #design: “Timing closure by design”, a high frequency microprocessor design methodology (SDP, NA, DB, PKC, SHD, BKF, HPH, NK, OK, KL, DM, KJN, JP, JP, JS, OT, PV), pp. 712–717.
DAC-2000-YenY #design #multi #verification: Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessor (JTY, QRY), pp. 718–723.
DAC-2000-EisnerSHNNV #design #hardware #protocol: A methodology for formal design of hardware control with application to cache coherence protocols (CE, IS, RH, WGN, KLN, KV), pp. 724–729.
DAC-2000-DrakeBGKPGSB: CGaAs PowerPC FXU (AJD, TDB, SMG, KLK, PNP, CRG, PSS, RBB), pp. 730–735.
DAC-2000-KanapkaPW #performance: Fast methods for extraction and sparsification of substrate coupling (JK, JRP, JW), pp. 738–743.
DAC-2000-KapurL #scalability: Large-scale capacitance calculation (SK, DEL), pp. 744–749.
DAC-2000-TsaiK #performance #reduction #simulation: Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction (CHT, SMK), pp. 750–755.
DAC-2000-DoughertyT #behaviour #design #physics #synthesis: Unifying behavioral synthesis and physical design (WED, DET), pp. 756–761.
DAC-2000-KatagiriYKHT #communication #concurrent #hardware #implementation #multi #protocol: Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization (HK, KY, AK, TH, KT), pp. 762–767.
DAC-2000-YuKW #representation #using: The use of carry-save representation in joint module selection and retiming (ZY, KYK, ANWJ), pp. 768–773.
DAC-2000-SaabHK: Closing the gap between analog and digital (KS, NBH, BK), pp. 774–779.
DAC-2000-KrishnaswamyCT #fault #simulation: A switch level fault simulation environment (VK, JC, TT), pp. 780–785.
DAC-2000-DwarakanathB #fault #simulation #tuple #using: Universal fault simulation using fault tuples (KND, RDB), pp. 786–789.
DAC-2000-ZachariahCR #algorithm #novel: A novel algorithm to extract two-node bridges (STZ, SC, CDR), pp. 790–793.
DAC-2000-RaoN #power management #using: Power minimization using control generated clocks (MSR, SKN), pp. 794–799.
DAC-2000-ChangKC #encoding #memory management #power management: Bus encoding for low-power high-performance memory systems (NC, KK, JC), pp. 800–805.
DAC-2000-LeeS #power management #realtime #runtime: Run-time voltage hopping for low-power real-time systems (SL, TS), pp. 806–809.
DAC-2000-QuKUP #estimation: Function-level power estimation methodology for microprocessors (GQ, NK, KU, MP), pp. 810–813.

Giovanni De MicheliProceedings of the 37th Design Automation ConferenceDAC, 2000.

Contents (149 items)

Giovanni De Micheli
Proceedings of the 37th Design Automation Conference
DAC, 2000.