BibSLEIGH — David

Travelled to:

1 × China
17 × USA
5 × France
5 × Germany

Collaborated with:

D.Sylvester V.Zolotov R.Panda K.Chopra T.N.Mudge A.Agarwal K.Agarwal D.Lee A.Srivastava R.G.Dreslinski S.B.K.Vrudhula V.Veetil R.Gandikota T.Edwards S.Sirichotiyakul R.R.Rao M.Seok R.Das C.Oh M.R.Becer A.Dharchoudhury V.Bertacco S.Hanson H.Deogun B.Thudi D.Fick K.Flautner R.Chaudhry B.Cline S.Sundareswaran V.Joshi A.Torres S.Das S.Shah T.M.Austin K.Gala J.Wang M.Zhao Y.Kim I.N.Hajj C.Zhuo A.DeOrio F.Dartu A.Das C.Chakrabarti S.Jeloka S.Satpathy J.Zuo R.Levy N.Abeyratne K.Sewell M.Woh Y.Chang L.Ding P.Tehrani E.Karl A.Devgan B.Zhai W.Kwong Y.Lee D.Yoon D.Jeon D.M.Bull R.Aitken S.Rochel H.Kaul S.Pant J.Norton D.G.Saab R.B.Mueller-Thuns J.A.Abraham J.T.Rahmeh S.Rao V.Sukharev J.Hu G.K.Chen S.W.Director F.Liu S.R.Nassif S.Lee B.Young S.S.Sapatnekar R.Vaidyanathan B.Tutuianu D.Bearden S.Gavrilov A.Glebov S.Rusakov L.G.Jones G.Vijayan Y.Kang N.R.Pinckney C.Chen Z.Zhang H.Naeimi S.Sandhu D.Kershaw M.Wieckowski V.Chandra S.Idgunji C.Pietrzyk R.C.Aitken I.Algor Q.Li B.Giridhar S.Seo Y.Park S.A.Mahlke J.M.Rabaey K.Bernstein J.Frenkil M.Horowitz W.Nebel T.Sakurai A.Yang G.Braca A.Dasgupta A.Grinshpon B.Orshav

Talks about:

analysi (19) power (16) circuit (12) model (12) design (10) leakag (9) time (9) statist (8) nois (8) base (8)

Person: David Blaauw

DBLP: Blaauw:David

Contributed to:

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

2000

1999

1998

1997

1989

Wrote 68 papers:

DAC-2014-AbeyratneJKBDDM: Quality-of-Service for a High-Radix Switch (NA, SJ, YK, DB, RGD, RD, TNM), p. 6.
DAC-2014-RaoJDBDM #named #performance: VIX: Virtual Input Crossbar for Efficient Switch Allocation (SR, SJ, RD, DB, RGD, TNM), p. 6.
HPCA-2013-AbeyratneDLSGDBM #scalability #symmetry #towards: Scaling towards kilo-core processors with asymmetric high-radix topologies (NA, RD, QL, KS, BG, RGD, DB, TNM), pp. 496–507.
DAC-2012-LeeKYBS #design #guidelines #power management: Circuit and system design guidelines for ultra-low power sensor nodes (YL, YK, DY, DB, DS), pp. 1037–1042.
DAC-2012-PinckneySDFMSB #performance: Assessing the performance limits of parallelized near-threshold computing (NRP, KS, RGD, DF, TNM, DS, DB), pp. 1147–1152.
DAC-2012-SatpathyDDMSB #multi #quality #self: High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service (SS, RD, RGD, TNM, DS, DB), pp. 406–411.
DAC-2012-SeoDWPCMBM #architecture #process: Process variation in near-threshold wide SIMD architectures (SS, RGD, MW, YP, CC, SAM, DB, TNM), pp. 980–987.
DAC-2011-SeokJCBS #design #energy #performance #pipes and filters: Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design (MS, DJ, CC, DB, DS), pp. 990–995.
DATE-2011-ChenKZBSNS: A confidence-driven model for error-resilient computing (CHC, YK, ZZ, DB, DS, HN, SS), pp. 1608–1613.
DATE-2011-WohSDKSBM #power management: Low power interconnects for SIMD computers (MW, SS, RGD, DK, DS, DB, TNM), pp. 600–605.
DAC-2010-JoshiSTASB #modelling: Closed-form modeling of layout-dependent mechanical stress (VJ, VS, AT, KA, DS, DB), pp. 673–678.
DAC-2010-VeetilCSB #monte carlo #performance #resource management: Efficient smart monte carlo based SSTA on graphics processing units with improved resource utilization (VV, YHC, DS, DB), pp. 793–798.
DATE-2010-WieckowskiSBCIPA #analysis #black box: A black box method for stability analysis of arbitrary SRAM cell structures (MW, DS, DB, VC, SI, CP, RCA), pp. 795–800.
DATE-2010-ZhuoSB #process #reliability: Process variation and temperature-aware reliability management (CZ, DS, DB), pp. 580–585.
DAC-2009-DasBBFA #design: Addressing design margins through error-tolerant circuits (SD, DB, DMB, KF, RA), pp. 11–12.
DAC-2009-FickDHBBS #named #network #reliability: Vicis: a reliable network for unreliable silicon (DF, AD, JH, VB, DB, DS), pp. 812–817.
DAC-2009-GandikotaDTB #modelling #worst-case: Worst-case aggressor-victim alignment with current-source driver models (RG, LD, PT, DB), pp. 13–18.
DAC-2009-VeetilSBSR #analysis #dependence #performance: Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence (VV, DS, DB, SS, SR), pp. 154–159.
DATE-2009-FickDCBSB #algorithm #fault tolerance: A highly resilient routing algorithm for fault-tolerant NoCs (DF, AD, GKC, VB, DS, DB), pp. 21–26.
DAC-2008-GandikotaBS #analysis #modelling #statistics: Modeling crosstalk in statistical static timing analysis (RG, DB, DS), pp. 974–979.
DAC-2008-JoshiCSBA #power management #reduction #using: Leakage power reduction using stress-enhanced layouts (VJ, BC, DS, DB, KA), pp. 912–917.
DAC-2008-VeetilSB #analysis #incremental #monte carlo #performance #statistics: Efficient Monte Carlo based incremental statistical timing analysis (VV, DS, DB), pp. 676–681.
DATE-2008-ClineCBTS #modelling: Transistor-Specific Delay Modeling for SSTA (BC, KC, DB, AT, SS), pp. 592–597.
DAC-2007-GandikotaCBSB #analysis #set: Top-k Aggressors Sets in Delay Noise Analysis (RG, KC, DB, DS, MRB), pp. 174–179.
DAC-2007-HansonSSB #scalability: Nanometer Device Scaling in Subthreshold Circuits (SH, MS, DS, DB), pp. 700–705.
DAC-2007-SeokHSB #analysis #design #optimisation: Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design (MS, SH, DS, DB), pp. 694–699.
DAC-2006-KarlBSM #modelling #reliability: Reliability modeling and management in dynamic microprocessor-based systems (EK, DB, DS, TNM), pp. 1057–1060.
DATE-2006-RaoCBS #algorithm #fault #performance: An efficient static algorithm for computing the soft error rates of combinational circuits (RRR, KC, DB, DS), pp. 164–169.
DAC-2005-AgarwalCBZ #analysis #optimisation #statistics #using: Circuit optimization using statistical static timing analysis (AA, KC, DB, VZ), pp. 321–324.
DAC-2005-BlaauwC #tool support: CAD tools for variation tolerance (DB, KC), p. 766.
DAC-2005-SrivastavaSASBD #correlation #estimation #parametricity #performance #power management: Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance (AS, SS, KA, DS, DB, SWD), pp. 535–540.
DATE-2005-AgarwalCB #optimisation #statistics #using: Statistical Timing Based Optimization using Gate Sizing (AA, KC, DB), pp. 400–405.
DATE-2005-KaulSBMA #design #fault: DVS for On-Chip Bus Designs Based on Timing Error Correction (HK, DS, DB, TNM, TMA), pp. 80–85.
DAC-2004-AgarwalDB #multi #statistics: Statistical gate delay model considering multiple input switching (AA, FD, DB), pp. 658–663.
DAC-2004-AgarwalSBLNV #analysis #metric: Variational delay metrics for interconnect timing analysis (KA, DS, DB, FL, SRN, SBKV), pp. 381–384.
DAC-2004-DeogunRSB #encoding #reduction: Leakage-and crosstalk-aware bus encoding for total power reduction (HD, RRR, DS, DB), pp. 779–782.
DAC-2004-LeeDBABM #architecture #simulation: Circuit-aware architectural simulation (SL, SD, VB, TMA, DB, TNM), pp. 305–310.
DAC-2004-LeeZB #analysis #using: Static timing analysis using backward signal propagation (DL, VZ, DB), pp. 664–669.
DAC-2004-PantBZSP #analysis #approach #grid #power management #probability: A stochastic approach To power grid analysis (SP, DB, VZ, SS, RP), pp. 171–176.
DAC-2004-RaoDBS #estimation #parametricity #variability: Parametric yield estimation considering leakage variability (RRR, AD, DB, DS), pp. 442–447.
DAC-2004-SrivastavaSB #optimisation #power management #process #statistics #using: Statistical optimization of leakage power considering process variations using dual-Vth and sizing (AS, DS, DB), pp. 773–778.
DAC-2004-SrivastavaSB04a #power management #using: Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment (AS, DS, DB), pp. 783–787.
DAC-2004-ZhaiBSF #scalability: Theoretical and practical limits of dynamic voltage scaling (BZ, DB, DS, KF), pp. 868–873.
DATE-v1-2004-LeeDBS #power management: Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization (DL, HD, DB, DS), pp. 494–499.
DATE-v1-2004-SrivastavaSB #concurrent #design #power management: Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design (AS, DS, DB), pp. 718–719.
DAC-2003-AgarwalBZV #bound #refinement #statistics: Computation and Refinement of Statistical Bounds on Circuit Delay (AA, DB, VZ, SBKV), pp. 348–353.
DAC-2003-AgarwalSB #effectiveness: An effective capacitance based driver output model for on-chip RLC interconnects (KA, DS, DB), pp. 376–381.
DAC-2003-AgarwalSB03a #metric: Simple metrics for slew rate of RC circuits based on two circuit moments (KA, DS, DB), pp. 950–953.
DAC-2003-BecerBAPOZH #reduction: Post-route gate sizing for crosstalk noise reduction (MRB, DB, IA, RP, CO, VZ, INH), pp. 954–957.
DAC-2003-LeeB #reduction: Static leakage reduction through simultaneous threshold voltage and state assignment (DL, DB), pp. 191–194.
DAC-2003-LeeKBS #analysis: Analysis and minimization techniques for total leakage considering gate oxide leakage (DL, WK, DB, DS), pp. 175–180.
DAC-2003-RabaeySBBFHNSY: Reshaping EDA for power (JMR, DS, DB, KB, JF, MH, WN, TS, AY), p. 15.
DAC-2003-ThudiB: Non-iterative switching window computation for delay-noise (BT, DB), pp. 390–395.
DATE-2003-AgarwalBZV #analysis #bound #statistics #using: Statistical Timing Analysis Using Bounds (AA, DB, VZ, SBKV), pp. 10062–10067.
DAC-2002-VrudhulaBS #estimation: Estimation of the likelihood of capacitive coupling noise (SBKV, DB, SS), pp. 653–658.
DATE-2002-BecerZBPH #analysis #using: Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model (MRB, VZ, DB, RP, INH), pp. 456–463.
DAC-2001-GalaBWZZ #analysis #design: Inductance 101: Analysis and Design Issues (KG, DB, JW, VZ, MZ), pp. 329–334.
DAC-2001-SirichotiyakulBOLZZ #modelling #worst-case: Driver Modeling and Alignment for Worst-Case Delay Noise (SS, DB, CO, RL, VZ, JZ), pp. 720–725.
DAC-2000-BlaauwPD #graph: Removing user specified false paths from timing graphs (DB, RP, AD), pp. 270–273.
DAC-2000-ChaudhryBPE #analysis: Current signature compression for IR-drop analysis (RC, DB, RP, TE), pp. 162–167.
DAC-2000-GalaZPYWB #analysis #modelling: On-chip inductance modeling and analysis (KG, VZ, RP, BY, JW, DB), pp. 63–68.
DAC-2000-LevyBBDGOOSZ #analysis #design #named: ClariNet: a noise analysis tool for deep submicron design (RL, DB, GB, AD, AG, CO, BO, SS, VZ), pp. 233–238.
DAC-2000-ZhaoPSECB #analysis #network: Hierarchical analysis of power distribution networks (MZ, RP, SSS, TE, RC, DB), pp. 150–155.
DAC-1999-SirichotiyakulEOZDPB #power management: Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing (SS, TE, CO, JZ, AD, RP, DB), pp. 436–441.
DAC-1998-DharchoudhuryPBVTB #analysis #design #network: Design and Analysis of Power Distribution Networks in PowerPC Microprocessors (AD, RP, DB, RV, BT, DB), pp. 738–743.
DAC-1998-PandaDENB #design #incremental #migration #named: Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization (RP, AD, TE, JN, DB), pp. 388–391.
EDTC-1997-GavrilovGRBJV #performance: Fast power loss calculation for digital static CMOS circuits (SG, AG, SR, DB, LGJ, GV), pp. 411–415.
DAC-1989-BlaauwSMAR #automation #behaviour #generative #modelling: Automatic Generation of Behavioral Models from Switch-Level Descriptions (DB, DGS, RBMT, JAA, JTR), pp. 179–184.