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Travelled to:
1 × USA
Collaborated with:
M.Ketkar S.S.Sapatnekar
Talks about:
transistor (1) convex (1) model (1) delay (1) size (1)

Person: Kishore Kasamsetty

DBLP DBLP: Kasamsetty:Kishore

Contributed to:

DAC 20002000

Wrote 1 papers:

DAC-2000-KetkarKS #modelling
Convex delay models for transistor sizing (MK, KK, SSS), pp. 655–660.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.