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Travelled to:
1 × USA
Collaborated with:
A.J.d.Geus J.B.Reed G.Wikle
Talks about:
interconnect (1) circuit (1) analysi (1) integr (1) delay (1) ida (1)

Person: M. Rekhson

DBLP DBLP: Rekhson:M=

Contributed to:

DAC 19841984

Wrote 1 papers:

DAC-1984-GeusRRW #analysis #named
IDA: Interconnect delay analysis for integrated circuits (AJdG, JBR, MR, GW), pp. 536–541.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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