Travelled to:4 × USA
Collaborated with:∅ K.Keutzer W.C.Rhines D.Gregory K.A.Bartlett G.D.Hachtel J.B.Reed M.Rekhson G.Wikle R.Dahlberg R.Bingham F.Bacchini G.Spirakis J.A.Carballo F.Hsu K.Yamada J.Vleeschhouwer W.East M.J.Fister J.Hu R.Cassidy
Talks about:optim (2) logic (2) eda (2) interconnect (1) differenti (1) megatrend (1) benchmark (1) synthesi (1) synthes (1) serious (1)
Person: Aart J. de Geus
DBLP: Geus:Aart_J=_de
Contributed to:
20072005200419861984Wrote 6 papers:
- DAC-2007-BacchiniSCKGHY #roadmap
- Megatrends and EDA 2017 (FB, GS, JAC, KK, AJdG, FCH, KY), pp. 21–22.
- DAC-2005-VleeschhouwerEFGRHC
- Differentiate and deliver: leveraging your partners (JV, WE, MJF, AJdG, WCR, JH, RC), p. 1.
- DAC-2004-DahlbergKBGR #named
- EDA: this is serious business (RD, KK, RB, AJdG, WCR), p. 1.
- DAC-1986-Geus #automation #benchmark #design #logic #metric #optimisation #synthesis
- Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference (AJdG), p. 78.
- DAC-1986-GregoryBGH #automation #logic #named #optimisation
- SOCRATES: a system for automatically synthesizing and optimizing combinational logic (DG, KAB, AJdG, GDH), pp. 79–85.
- DAC-1984-GeusRRW #analysis #named
- IDA: Interconnect delay analysis for integrated circuits (AJdG, JBR, MR, GW), pp. 536–541.