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Travelled to:
1 × Croatia
1 × Finland
1 × Germany
1 × Hungary
1 × Ireland
1 × The Netherlands
1 × Vietnam
3 × Italy
4 × France
Collaborated with:
S.Crespi-Reghizzi M.Rossi A.Morzenti P.S.Pietro D.Mandrioli V.Lonati C.A.Furia F.Panella M.M.Bersani A.Barenghi P.Colombo P.Spoletini A.Coen-Porisini E.Viviani L.Cavallaro A.Frigeri
Talks about:
time (6) model (5) specif (4) verif (4) check (4) languag (3) system (3) preced (3) real (3) oper (3)

Person: Matteo Pradella

DBLP DBLP: Pradella:Matteo

Contributed to:

CC 20142014
DLT 20132013
SLE 20122012
CIAA 20112011
SEFM 20102010
FM 20092009
SEFM 20092009
ASE 20082008
FM 20082008
ESEC/FSE 20072007
SAC 20062006
DLT 20032003
FME 20032003
ICSE 20002000
AFL 20172017

Wrote 15 papers:

CC-2014-BarenghiCMPP #generative
The PAPAGENO Parallel-Parser Generator (AB, SCR, DM, FP, MP), pp. 192–196.
DLT-2013-PanellaPLM #precedence
Operator Precedence ω-Languages (FP, MP, VL, DM), pp. 396–408.
SLE-2012-BarenghiVCMP #generative #named #parallel #parsing #precedence
PAPAGENO: A Parallel Parser Generator for Operator Precedence Grammars (AB, EV, SCR, DM, MP), pp. 264–274.
CIAA-2011-LonatiP #2d #automaton #towards
Towards More Expressive 2D Deterministic Automata (VL, MP), pp. 225–237.
SEFM-2010-BersaniCFPR #constraints #integer #ltl #runtime #smt #specification #verification
SMT-based Verification of LTL Specification with Integer Constraints and its Application to Runtime Checking of Service Substitutability (MMB, LC, AF, MP, MR), pp. 244–254.
FM-2009-PradellaMP #bound #encoding #metric #model checking
A Metric Encoding for Bounded Model Checking (MP, AM, PSP), pp. 741–756.
SEFM-2009-BersaniFPR #modelling #multi #paradigm #realtime #verification
Integrated Modeling and Verification of Real-Time Systems through Multiple Paradigms (MMB, CAF, MP, MR), pp. 13–22.
ASE-2008-PradellaMP #bound #realtime #satisfiability #specification
Refining Real-Time System Specifications through Bounded Model- and Satisfiability-Checking (MP, AM, PSP), pp. 119–127.
FM-2008-FuriaPR #approximate #automation #specification #verification
Automated Verification of Dense-Time MTL Specifications Via Discrete-Time Approximation (CAF, MP, MR), pp. 132–147.
ESEC-FSE-2007-PradellaMP #symmetry #verification
The symmetry of the past and of the future: bi-infinite time in the verification of temporal properties (MP, AM, PSP), pp. 312–320.
SAC-2006-ColomboPR #architecture #formal method #modelling #realtime #uml
A UML 2-compatible language and tool for formal modeling real-time system architectures (PC, MP, MR), pp. 1785–1790.
DLT-2003-ReghizziP
Tile Rewriting Grammars (SCR, MP), pp. 206–217.
FME-2003-MorzentiPPS #model checking #specification
Model-Checking TRIO Specifications in SPIN (AM, MP, PSP, PS), pp. 542–561.
ICSE-2000-PradellaRMC #approach #corba #design #formal method
A formal approach for designing CORBA based applications (MP, MR, DM, ACP), pp. 188–197.
AFL-2017-CrespiReghizziP #higher-order #precedence
Higher-order Operator Precedence Languages (SCR, MP), pp. 86–100.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.