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Travelled to:
1 × Germany
Collaborated with:
R.Yuan J.Schleicher G.Baeckler S.Cheung K.K.Chua H.K.Phoo
Talks about:
methodolog (1) synthesi (1) structur (1) verif (1) fpga (1) asic (1)

Person: Michael Hutton

DBLP DBLP: Hutton:Michael

Contributed to:

DATE Designers’ Forum 20062006

Wrote 1 papers:

DATE-DF-2006-HuttonYSBCCP #synthesis #verification
A methodology for FPGA to structured-ASIC synthesis and verification (MH, RY, JS, GB, SC, KKC, HKP), pp. 64–69.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.