Travelled to:3 × USA
Collaborated with:Y.Lichtenstein M.Rimon S.Copty I.Jaeger Y.Katz M.L.Behm J.M.Ludden A.Adir Y.Arbetman B.Dubrov M.A.Calligaro A.Cofler G.Duffy
Talks about:generat (2) verif (2) test (2) processor (1) interleav (1) scenario (1) parallel (1) intellig (1) industri (1) approach (1)
Person: Michael Vinov
DBLP: Vinov:Michael
Contributed to:
200720052004Wrote 3 papers:
- DAC-2007-CoptyJKV #approach #generative #novel #testing
- Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation (SC, IJ, YK, MV), pp. 891–895.
- DAC-2005-AdirADLRVCCD #case study #named #parallel #verification
- VLIW: a case study of parallelism verification (AA, YA, BD, YL, MR, MV, MAC, AC, GD), pp. 779–782.
- DAC-2004-BehmLLRV #experience #generative #industrial #testing #verification
- Industrial experience with test generation languages for processor verification (MLB, JML, YL, MR, MV), pp. 36–40.