BibSLEIGH — Proceedings of the 41st Design Automation Conference

Sharad Malik, Limor Fix, Andrew B. Kahng
Proceedings of the 41st Design Automation Conference
DAC, 2004.

SYS

@proceedings{DAC-2004,
	acmid         = "996566",
	address       = "San Diego, California, USA",
	editor        = "Sharad Malik and Limor Fix and Andrew B. Kahng",
	isbn          = "1-58113-828-8",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 41st Design Automation Conference}",
	year          = 2004,
}

Contents (197 items)

DAC-2004-DahlbergKBGR #named: EDA: this is serious business (RD, KK, RB, AJdG, WCR), p. 1.
DAC-2004-VassighiKNSYLCSD #design #optimisation: Design optimizations for microprocessors at low temperature (AV, AK, SN, GS, YY, SL, GC, MS, VD), pp. 2–5.
DAC-2004-AgarwalKMR #design: Leakage in nano-scale technologies: mechanisms, impact and design considerations (AA, CHK, SM, KR), pp. 6–11.
DAC-2004-HeLS #reduction: System level leakage reduction considering the interdependence of temperature and leakage (LH, WL, MRS), pp. 12–17.
DAC-2004-RajaramHM #variability: Reducing clock skew variability via cross links (AR, JH, RNM), pp. 18–23.
DAC-2004-AlpertHHQ #flexibility #layout #performance #physics: Fast and flexible buffer trees that navigate the physical layout environment (CJA, MH, JH, STQ), pp. 24–29.
DAC-2004-LiuPP #library #power management #question #what: Practical repeater insertion for low power: what repeater library do we need? (XL, YP, MCP), pp. 30–35.
DAC-2004-BehmLLRV #experience #generative #industrial #testing #verification: Industrial experience with test generation languages for processor verification (MLB, JML, YL, MR, MV), pp. 36–40.
DAC-2004-AsafMZ #analysis #functional: Defining coverage views to improve functional coverage analysis (SA, EM, AZ), pp. 41–44.
DAC-2004-KwonKK #functional #graph #metric #synthesis: Systematic functional coverage metric synthesis from hierarchical temporal event relation graph (YSK, YIK, CMK), pp. 45–48.
DAC-2004-FineUZ #functional #probability #verification: Probabilistic regression suites for functional verification (SF, SU, AZ), pp. 49–54.
DAC-2004-RosenbandA #composition #scheduling: Modular scheduling of guarded atomic actions (DLR, A), pp. 55–60.
DAC-2004-KappS #automation #behaviour #control flow #scheduling #synthesis: Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis (KK, VKS), pp. 61–66.
DAC-2004-MoB #design: A timing-driven module-based chip design flow (FM, RKB), pp. 67–70.
DAC-2004-EdmanS #design: Timing closure through a globally synchronous, timing partitioned design methodology (AE, CS), pp. 71–74.
DAC-2004-BorkarKD #challenge #design #reliability: Design and reliability challenges in nanometer technologies (SB, TK, VD), p. 75.
DAC-2004-Shanbhag #design #paradigm #reliability: A communication-theoretic design paradigm for reliable SOCs (NRS), p. 76.
DAC-2004-Micheli #communication #reliability: Reliable communication in systems on chips (GDM), p. 77.
DAC-2004-Austin #architecture #design #robust: Designing robust microarchitectures (TMA), p. 78.
DAC-2004-Iyer #detection #fault: Hierarchical application aware error detection and recovery (RKI), p. 79.
DAC-2004-StrojwasCGHKLNPT #fault #question: When IC yield missed the target, who is at fault? (AJS, MC, VG, JH, JK, ML, WN, DP, MT), p. 80.
DAC-2004-LyuhK #energy #memory management #multi #scheduling: Memory access scheduling and binding considering energy minimization in multi-bank memory systems (CGL, TK), pp. 81–86.
DAC-2004-SeoKC #realtime #scheduling: Profile-based optimal intra-task voltage scheduling for hard real-time applications (JS, TK, KSC), pp. 87–92.
DAC-2004-CarballoNYVCN #adaptation #design: Requirement-based design methods for adaptive communications links (JAC, KJN, SMY, IV, CC, VRN), pp. 93–98.
DAC-2004-MuttrejaRRJ #automation #embedded #energy #megamodelling #performance: Automated energy/performance macromodeling of embedded software (AM, AR, SR, NKJ), pp. 99–102.
DAC-2004-SridharaS #framework #network: Coding for system-on-chip networks: a unified framework (SRS, NRS), pp. 103–106.
DAC-2004-SchueleS #abstraction #analysis #assembly #execution #source code: Abstraction of assembler programs for symbolic worst case execution time analysis (TS, KS), pp. 107–112.
DAC-2004-PasrichaDB #approach #architecture #communication #modelling #performance #transaction: Extending the transaction level modeling approach for fast communication architecture exploration (SP, NDD, MBR), pp. 113–118.
DAC-2004-ResanoM #configuration management #hardware #scheduling: Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware (JR, DM), pp. 119–124.
DAC-2004-Kandemir #multi #named #scheduling: LODS: locality-oriented dynamic scheduling for on-chip multiprocessors (MTK), pp. 125–128.
DAC-2004-BrandoleseFS #design #estimation: An area estimation methodology for FPGA based designs at systemc-level (CB, WF, FS), pp. 129–132.
DAC-2004-VanderhaegenB #automation #design #geometry #programming #using: Automated design of operational transconductance amplifiers using reversed geometric programming (JPV, RWB), pp. 133–138.
DAC-2004-BhattacharyaJHS #design #scalability: Correct-by-construction layout-centric retargeting of large analog designs (SB, NJ, RH, CJRS), pp. 139–144.
DAC-2004-AgarwalSYV #modelling #performance: Fast and accurate parasitic capacitance models for layout-aware (AA, HS, VY, RV), pp. 145–150.
DAC-2004-XuPB #layout #named #optimisation: ORACLE: optimization with recourse of analog circuits including layout extraction (YX, LTP, SPB), pp. 151–154.
DAC-2004-ZhangDRRC #performance #synthesis #towards: A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits (GZ, EAD, RAR, RAR, LRC), pp. 155–158.
DAC-2004-WangM #constraints #power management: Buffer sizing for clock power minimization subject to general skew constraints (KW, MMS), pp. 159–164.
DAC-2004-ZhaoFZSP #power management: Optimal placement of power supply pads and pins (MZ, YF, VZ, SS, RP), pp. 165–170.
DAC-2004-PantBZSP #analysis #approach #grid #power management #probability: A stochastic approach To power grid analysis (SP, DB, VZ, SS, RP), pp. 171–176.
DAC-2004-WuC #analysis #design #network #performance: Efficient power/ground network analysis for power integrity-driven design methodology (SWW, YWC), pp. 177–180.
DAC-2004-JerkeLS #design #layout: Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs (GJ, JL, JS), pp. 181–184.
DAC-2004-DeoZBCGLRRS #question #what: What happened to ASIC?: Go (recon)figure? (ND, BZ, IB, JC, BG, PL, CBR, CR, RS), p. 185.
DAC-2004-HuangW #proximity: Optical proximity correction (OPC): friendly maze routing (LDH, MDFW), pp. 186–191.
DAC-2004-ShenoyKC #automation #design #programmable: Design automation for mask programmable fabrics (NVS, JK, RC), pp. 192–197.
DAC-2004-RanM #configuration management #design #on the: On designing via-configurable cell blocks for regular fabrics (YR, MMS), pp. 198–203.
DAC-2004-KheterpalSP #architecture: Routing architecture exploration for regular fabrics (VK, AJS, LTP), pp. 204–207.
DAC-2004-YoshidaDB #estimation #standard: Accurate pre-layout estimation of standard cell characteristics (HY, KD, VB), pp. 208–211.
DAC-2004-ParthasarathyICW #constraints #performance #theorem proving: An efficient finite-domain constraint solver for circuits (GP, MKI, KTC, LCW), pp. 212–217.
DAC-2004-AndrausS #abstraction #automation #modelling #verification: Automatic abstraction and verification of verilog models (ZSA, KAS), pp. 218–223.
DAC-2004-MangH #abstraction #analysis #refinement: Abstraction refinement by controllability and cooperativeness analysis (FYCM, PHH), pp. 224–229.
DAC-2004-LuJ #using #verification: Verifying a gigabit ethernet switch using SMV (YL, MJ), pp. 230–233.
DAC-2004-ShehataA #composition #verification: A general decomposition strategy for verifying register renaming (HIS, MA), pp. 234–237.
DAC-2004-FrancescoMABCM #approach #hardware #runtime: An integrated hardware/software approach for run-time scratchpad management (FP, PM, DA, LB, FC, JMM), pp. 238–243.
DAC-2004-NettoACA #multi: Multi-profile based code compression (EWN, RA, PC, GA), pp. 244–249.
DAC-2004-HanBBCJ #architecture #data transfer #distributed #flexibility #memory management #multi #performance #scalability: An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory (SIH, AB, MB, SIC, AAJ), pp. 250–255.
DAC-2004-NolletMVMV #network: Operating-system controlled network on chip (VN, TM, DV, JYM, SV), pp. 256–259.
DAC-2004-HuM #named: DyAD: smart routing for networks-on-chip (JH, RM), pp. 260–263.
DAC-2004-SentovichALR #industrial: Competitive strategies for the electronics industry (ES, JA, PL, BR), p. 264.
DAC-2004-SentovichCDK #modelling: Business models in IP, software licensing, and services (ES, RC, JD, AK), p. 264.
DAC-2004-Kung #design: Timing closure for low-FO4 microprocessor design (DSK), pp. 265–266.
DAC-2004-Rodman #question: Forest vs. trees: where’s the slack? (PKR), p. 267.
DAC-2004-VujkovicWSS #performance: Efficient timing closure without timing driven placement and routing (MV, DW, WS, CS), pp. 268–273.
DAC-2004-BacchiniDBBNIY #named #verification #what: Verification: what works and what doesn’t (FB, RFD, BB, KB, KN, MI, EY), p. 274.
DAC-2004-JejurikarPG #embedded #realtime #scalability: Leakage aware dynamic voltage scaling for real-time embedded systems (RJ, CP, RKG), pp. 275–280.
DAC-2004-CaiGG #agile #design #profiling: Retargetable profiling for rapid, early system-level design space exploration (LC, AG, DG), pp. 281–286.
DAC-2004-PieperMPTK #multi #simulation: High level cache simulation for heterogeneous multiprocessors (JJP, AM, JMP, DET, FK), pp. 287–292.
DAC-2004-KimYKK #functional #hardware #performance #simulation: Communication-efficient hardware acceleration for fast functional simulation (YIK, WSY, YSK, CMK), pp. 293–298.
DAC-2004-NakamuraHKYY #c #c++ #communication #hardware #performance #using: A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication (YN, KH, IK, KY, TY), pp. 299–304.
DAC-2004-LeeDBABM #architecture #simulation: Circuit-aware architectural simulation (SL, SD, VB, TMA, DB, TNM), pp. 305–310.
DAC-2004-CapodieciGKSY #design #towards: Toward a methodology for manufacturability-driven design rule exploration (LC, PG, ABK, DS, JY), pp. 311–316.
DAC-2004-McCullen: Phase correct routing for alternating phase shift masks (KWM), pp. 317–320.
DAC-2004-GuptaH #towards: Toward a systematic-variation aware timing methodology (PG, FLH), pp. 321–326.
DAC-2004-GuptaKSS #effectiveness #runtime: Selective gate-length biasing for cost-effective runtime leakage control (PG, ABK, PS, DS), pp. 327–330.
DAC-2004-VisweswariahRKWN #analysis #first-order #incremental #statistics: First-order incremental block-based statistical timing analysis (CV, KR, KK, SGW, SN), pp. 331–336.
DAC-2004-OrshanskyB #analysis #correlation #performance #statistics: Fast statistical timing analysis handling arbitrary delay correlations (MO, AB), pp. 337–342.
DAC-2004-LeLP #analysis #correlation #named #statistics: STAC: statistical timing analysis with correlation (JL, XL, LTP), pp. 343–348.
DAC-2004-BacchiniPBPBCB #design #industrial: System level design: six success stories in search of an industry (FB, PGP, RAB, RP, AB, RC, MBR), pp. 349–350.
DAC-2004-XiuMFR #scalability: Large-scale placement by grid-warping (ZX, JDZM, SMF, RAR), pp. 351–356.
DAC-2004-KahngR #concept #feedback: Placement feedback: a concept and method for better min-cut placements (ABK, SR), pp. 357–362.
DAC-2004-AntonelliCDHKKMN #automaton #clustering #modelling #problem: Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions (DAA, DZC, TJD, XSH, ABK, PMK, RCM, MTN), pp. 363–368.
DAC-2004-WongBK #performance #reduction: Passivity-preserving model reduction via a computationally efficient project-and-balance scheme (NW, VB, CKK), pp. 369–374.
DAC-2004-WangHL #linear #nondeterminism #parametricity: A linear fractional transform (LFT) based model for interconnect parametric uncertainty (JMW, OH, JL), pp. 375–380.
DAC-2004-AgarwalSBLNV #analysis #metric: Variational delay metrics for interconnect timing analysis (KA, DS, DB, FL, SRN, SBKV), pp. 381–384.
DAC-2004-SilveiraP #algorithm #network #reduction: Exploiting input information in a model reduction algorithm for massively coupled parasitic networks (LMS, JRP), pp. 385–388.
DAC-2004-MittalZTB #automation: Automatic translation of software binaries onto FPGAs (GM, DZ, XT, PB), pp. 389–394.
DAC-2004-BriskKS #configuration management #design #set #synthesis: Area-efficient instruction set synthesis for reconfigurable system-on-chip designs (PB, AK, MS), pp. 395–400.
DAC-2004-OzturkKDCI #behaviour: Data compression for improving SPM behavior (ÖÖ, MTK, ID, GC, MJI), pp. 401–406.
DAC-2004-Smith #challenge #design #framework #platform #question: Platform based design: does it answer the entire SoC challenge? (GS), p. 407.
DAC-2004-Hopkins #approach #framework #mobile #multi #platform: Nomadic platform approach for wireless mobile multimedia (MH), p. 408.
DAC-2004-Sangiovanni-VincentelliCBS #challenge #design #platform: Benefits and challenges for platform-based design (ALSV, LPC, FDB, MS), pp. 409–414.
DAC-2004-Baron #configuration management #platform #roadmap #using: Trends in the use of re-configurable platforms (MB), p. 415.
DAC-2004-BaneresCK #paradigm #recursion: A recursive paradigm to solve Boolean relations (DB, JC, MK), pp. 416–421.
DAC-2004-SalujaK #algorithm #approximate #robust: A robust algorithm for approximate compatible observability don’t care (CODC) computation (NS, SPK), pp. 422–427.
DAC-2004-SasaoM #logic #multi: A method to decompose multiple-output logic functions (TS, MM), pp. 428–433.
DAC-2004-WangC #detection #symmetry: Symmetry detection for incompletely specified functions (KHW, JHC), pp. 434–437.
DAC-2004-KravetsK #optimisation: Implicit enumeration of structural changes in circuit optimization (VNK, PK), pp. 438–441.
DAC-2004-RaoDBS #estimation #parametricity #variability: Parametric yield estimation considering leakage variability (RRR, AD, DB, DS), pp. 442–447.
DAC-2004-RajVW #process: A methodology to improve timing yield in the presence of process variations (SR, SBKV, JMW), pp. 448–453.
DAC-2004-ChoiPR #algorithm #novel #process: Novel sizing algorithm for yield improvement under process variation in nanometer technology (SHC, BCP, KR), pp. 454–459.
DAC-2004-NajmM #analysis #statistics: Statistical timing analysis based on a timing yield model (FNN, NM), pp. 460–465.
DAC-2004-DebJO #design #modelling #paradigm #transaction: System design for DSP applications in transaction level modeling paradigm (AKD, AJ, JÖ), pp. 466–471.
DAC-2004-WuZN #approach #estimation: An analytical approach for dynamic range estimation (BW, JZ, FNN), pp. 472–477.
DAC-2004-ShiB #automation #communication #data type #fixpoint #optimisation: Automated fixed-point data-type optimization tool for signal processing and communication systems (CS, RWB), pp. 478–483.
DAC-2004-RoyB #algorithm #design #fixpoint #float #matlab: An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design (SR, PB), pp. 484–487.
DAC-2004-MohiyuddinPAW: Synthesizing interconnect-efficient low density parity check codes (MM, AP, AA, WW), pp. 488–491.
DAC-2004-WangMCA #learning #on the: On path-based learning and its applications in delay test and diagnosis (LCW, TMM, KTC, MSA), pp. 492–497.
DAC-2004-GoldmanKBBBCSV #question #statistics: Is statistical timing statistically significant? (RG, KK, CB, AB, SYB, EC, LS, CV), p. 498.
DAC-2004-VermaDS #online #performance #testing: Efficient on-line testing of FPGAs with provable diagnosabilities (VV, SD, VS), pp. 498–503.
DAC-2004-LiRP #fault #generative #on the #testing: On test generation for transition faults with minimized peak power dissipation (WL, SMR, IP), pp. 504–509.
DAC-2004-ParkCYC #power management #testing: A new state assignment technique for testing and low power (SP, SC, SY, MJC), pp. 510–513.
DAC-2004-VermeulenUG #automation #debugging #generative #hardware: Automatic generation of breakpoint hardware for silicon debug (BV, MZU, SKG), pp. 514–517.
DAC-2004-OhMASM #named #satisfiability: AMUSE: a minimally-unsatisfiable subformula extractor (YO, MNM, ZSA, KAS, ILM), pp. 518–523.
DAC-2004-ChauhanCK #algorithm #satisfiability #simulation: A SAT-based algorithm for reparameterization in symbolic simulation (PC, EMC, DK), pp. 524–529.
DAC-2004-DargaLSM #detection #symmetry: Exploiting structure in symmetry detection for CNF (PTD, MHL, KAS, ILM), pp. 530–534.
DAC-2004-WangJHS #bound #model checking #satisfiability: Refining the SAT decision ordering for bounded model checking (CW, HJ, GDH, FS), pp. 535–538.
DAC-2004-AnastasakisMP #equivalence #performance: Efficient equivalence checking with partitions and hierarchical cut-points (DA, LM, SP), pp. 539–542.
DAC-2004-RawatJJDGPMHS: Were the good old days all that good?: EDA then and now (SR, WHJJ, JAD, DG, POP, HDM, CH, JS), p. 543.
DAC-2004-ChoiSP #scalability: Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding (KC, RS, MP), pp. 544–549.
DAC-2004-ZhangDC #distributed #embedded #energy #fault tolerance #realtime: Energy-aware deterministic fault tolerance in distributed real-time embedded systems (YZ, RPD, KC), pp. 550–555.
DAC-2004-KejariwalGNDG #algorithm #clustering #energy #mobile: Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices (AK, SG, AN, ND, RG), pp. 556–561.
DAC-2004-HuM04a #adaptation #clustering #multi: Adaptive data partitioning for ambient multimedia (XH, RM), pp. 562–565.
DAC-2004-ChoudhuriM #embedded #energy: Energy characterization of filesystems for diskless embedded systems (SC, RNM), pp. 566–569.
DAC-2004-NookalaS: A method for correcting the functionality of a wire-pipelined circuit (VN, SSS), pp. 570–575.
DAC-2004-CasuM #approach #design #latency: A new approach to latency insensitive design (MRC, LM), pp. 576–581.
DAC-2004-LiuM #estimation: Pre-layout wire length and congestion estimation (QL, MMS), pp. 582–587.
DAC-2004-DavareLKS #implementation #performance #specification: The best of both worlds: the efficient asynchronous implementation of synchronous specifications (AD, KL, AK, ALSV), pp. 588–591.
DAC-2004-JeongN #detection #performance: Fast hazard detection in combinational circuits (CJ, SMN), pp. 592–595.
DAC-2004-JacomeHVB #design #fault #paradigm #probability: Defect tolerant probabilistic design paradigm for nanotechnologies (MFJ, CH, GdV, SB), pp. 596–601.
DAC-2004-CongFZ #architecture #automation #pipes and filters #synthesis: Architecture-level synthesis for automatic interconnect pipelining (JC, YF, ZZ), pp. 602–607.
DAC-2004-AbdiG #architecture #automation #functional #generative #specification: Automatic generation of equivalent architecture model from functional specification (SA, DG), pp. 608–613.
DAC-2004-YangKM #architecture #named #optimisation: Divide-and-concatenate: an architecture level optimization technique for universal hash functions (BY, RK, DAM), pp. 614–617.
DAC-2004-ContiCVOT #algorithm #analysis #performance: Performance analysis of different arbitration algorithms of the AMBA AHB bus (MC, MC, GBV, SO, CT), pp. 618–621.
DAC-2004-KorsmeyerZG #design #tool support: Design tools for BioMEMS (TK, JZ, KG), pp. 622–628.
DAC-2004-White #challenge #design: CAD challenges in BioMEMS design (JW), pp. 629–632.
DAC-2004-RutenbarBMPPSW #question: Will Moore’s Law rule in the land of analog? (RAR, ARB, THYM, EP, RP, CS, JW), p. 633.
DAC-2004-EkpanyapongMWLL #architecture #design: Profile-guided microarchitectural floorplanning for deep submicron processor design (ME, JRM, TW, HHSL, SKL), pp. 634–639.
DAC-2004-LongSLH #optimisation #pipes and filters: Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects (CL, LJS, WL, LH), pp. 640–645.
DAC-2004-LiYYYL #adaptation #algorithm #design #representation #using: A packing algorithm for non-manhattan hexagon/triangle placement design by using an adaptive o-tree representation (JL, TY, BY, JY, CL), pp. 646–651.
DAC-2004-KouroussisAN #power management #worst-case: Worst-case circuit delay taking into account power supply variations (DK, RA, FNN), pp. 652–657.
DAC-2004-AgarwalDB #multi #statistics: Statistical gate delay model considering multiple input switching (AA, FD, DB), pp. 658–663.
DAC-2004-LeeZB #analysis #using: Static timing analysis using backward signal propagation (DL, VZ, DB), pp. 664–669.
DAC-2004-ClabesFSDCPDMPFSLGWSRGRKMD #design #implementation: Design and implementation of the POWER5 microprocessor (JGC, JF, MS, JD, SGC, DWP, JD, PM, LP, MSF, BS, ML, MG, JW, NSS, SLR, GG, PR, RNK, JM, JSD), pp. 670–672.
DAC-2004-TakayanagiSPSL: A dual-core 64b ultraSPARC microprocessor for dense server applications (TT, JLS, BP, JS, ASL), pp. 673–677.
DAC-2004-DeleganesBGKSW #integer #logic: Low voltage swing logic circuits for a Pentium 4 processor integer core (DJD, MB, GG, KK, APS, SW), pp. 678–680.
DAC-2004-Wolf #future of #multi: The future of multiprocessor systems-on-chips (WW), pp. 681–685.
DAC-2004-KogelM #energy: Heterogeneous MP-SoC: the solution to energy-efficient signal processing (TK, HM), pp. 686–691.
DAC-2004-RowenL #architecture #flexibility: Flexible architectures for engineering successful SOCs (CR, SL), pp. 692–697.
DAC-2004-SaxenaH #modelling: Modeling repeaters explicitly within analytical placement (PS, BH), pp. 699–704.
DAC-2004-ObermeierJ #polynomial #using: Quadratic placement using an improved timing model (BO, FMJ), pp. 705–710.
DAC-2004-HrkicLB #approach #logic #replication: An approach to placement-coupled logic replication (MH, JL, GB), pp. 711–716.
DAC-2004-BraunNSCHSLM #approach #consistency #design #flexibility #novel: A novel approach for flexible and consistent ADL-driven ASIP design (GB, AN, WS, JC, MH, HS, RL, HM), pp. 717–722.
DAC-2004-YuM #embedded: Characterizing embedded applications for instruction-set extensible processors (PY, TM), pp. 723–728.
DAC-2004-BiswasCAPID #memory management #set: Introduction of local memory elements in instruction set extensions (PB, VC, KA, LP, PI, ND), pp. 729–734.
DAC-2004-LiLH #configuration management #reduction #using: FPGA power reduction using configurable dual-Vdd (FL, YL, LH), pp. 735–740.
DAC-2004-SelvakkumaranRRK #algorithm #clustering #multi: Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources (NS, AR, SR, GK), pp. 741–746.
DAC-2004-OhbaT #design #embedded #using: An SoC design methodology using FPGAs and embedded microprocessors (NO, KT), pp. 747–752.
DAC-2004-RaviKLMR #design #embedded #security: Security as a new dimension in embedded system design (SR, PCK, RBL, GM, AR), pp. 753–760.
DAC-2004-SultaniaSS #trade-off: Tradeoffs between date oxide leakage and delay for dual Tox circuits (AKS, DS, SSS), pp. 761–766.
DAC-2004-ChopraV #algorithm #pseudo: Implicit pseudo boolean enumeration algorithms for input vector control (KC, SBKV), pp. 767–772.
DAC-2004-SrivastavaSB #optimisation #power management #process #statistics #using: Statistical optimization of leakage power considering process variations using dual-Vth and sizing (AS, DS, DB), pp. 773–778.
DAC-2004-DeogunRSB #encoding #reduction: Leakage-and crosstalk-aware bus encoding for total power reduction (HD, RRR, DS, DB), pp. 779–782.
DAC-2004-SrivastavaSB04a #power management #using: Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment (AS, DS, DB), pp. 783–787.
DAC-2004-YanSS #3d #multi: Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics (SY, VS, WS), pp. 788–793.
DAC-2004-GopeCJ #matrix #modelling #multi #performance #rank: A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS (DG, SC, VJ), pp. 794–799.
DAC-2004-GuptaP #evaluation #named: CHIME: coupled hierarchical inductance model evaluation (SG, LTP), pp. 800–805.
DAC-2004-KapurL #scalability #simulation: Large-scale full-wave simulation (SK, DEL), pp. 806–809.
DAC-2004-TanjiA #analysis #distributed: Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects (YT, HA), pp. 810–813.
DAC-2004-ChangHW: Re-synthesis for delay variation tolerance (SCC, CTH, KCW), pp. 814–819.
DAC-2004-CaoK #logic #optimisation: Post-layout logic optimization of domino circuits (AC, CKK), pp. 820–825.
DAC-2004-TummeltshammerHP #constant #multi: Multiple constant multiplication by time-multiplexed mapping of addition chains (PT, JCH, MP), pp. 826–829.
DAC-2004-KapoorJ #concurrent #logic #specification #synthesis: Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis (HKK, MBJ), pp. 830–833.
DAC-2004-Kerntopf #algorithm #heuristic #logic #synthesis: A new heuristic algorithm for reversible logic synthesis (PK), pp. 834–837.
DAC-2004-HungSYYP #analysis #logic #quantum #reachability #synthesis: Quantum logic synthesis by symbolic reachability analysis (WNNH, XS, GY, JY, MAP), pp. 838–841.
DAC-2004-LiXLGP #approach #simulation: A frequency relaxation approach for analog/RF system-level simulation (XL, YX, PL, PG, LTP), pp. 842–847.
DAC-2004-MeiRCHD #performance #robust: Robust, stable time-domain methods for solving MPDEs of fast/slow systems (TM, JSR, TSC, SAH, DMD), pp. 848–853.
DAC-2004-PlasBVDWDGM #simulation: High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects (GVdP, MB, GV, PD, PW, SD, GGEG, HDM), pp. 854–859.
DAC-2004-TanGQ #analysis #approach #scalability: Hierarchical approach to exact symbolic analysis of large analog circuits (SXDT, WG, ZQ), pp. 860–863.
DAC-2004-YangM #adaptation #higher-order #modelling: An Essentially Non-Oscillatory (ENO) high-order accurate Adaptive table model for device modeling (BY, BM), pp. 864–867.
DAC-2004-ZhaiBSF #scalability: Theoretical and practical limits of dynamic voltage scaling (BZ, DB, DS, KF), pp. 868–873.
DAC-2004-TaylorS #array #energy #performance: Enabling energy efficiency in via-patterned gate array devices (RRT, HS), pp. 874–878.
DAC-2004-HuangSSSGV #design #modelling: Compact thermal modeling for temperature-aware design (WH, MRS, KS, KS, SG, SV), pp. 878–883.
DAC-2004-BasuLWMB #optimisation #power management: Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era (AB, SCL, VW, AM, KB), pp. 884–887.
DAC-2004-KanjLAR: Noise characterization of static CMOS gates (RK, TL, BA, ER), pp. 888–893.
DAC-2004-ZhaoBD #analysis #scalability: A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits (CZ, XB, SD), pp. 894–899.
DAC-2004-DingM #logic #novel: A novel technique to improve noise immunity of CMOS dynamic logic circuits (LD, PM), pp. 900–903.
DAC-2004-ZhangHC #analysis #pipes and filters #statistics: Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining (LZ, YH, CCPC), pp. 904–907.
DAC-2004-YoussefYSPJ #case study #debugging #design #interface #video: Debugging HW/SW interface for MPSoC: video encoder system design case study (MWY, SY, AS, YP, AAJ), pp. 908–913.
DAC-2004-MuraliM #automation #generative #named: SUNMAP: a tool for automatic topology selection and generation for NoCs (SM, GDM), pp. 914–919.
DAC-2004-ChengTM #embedded #named #synthesis: FITS: framework-based instruction-set tuning synthesis for embedded application specific processors (ACC, GST, TNM), pp. 920–923.
DAC-2004-KulkarniBS #domain-specific language #framework #platform: Mapping a domain specific language to a platform FPGA (CK, GJB, GS), pp. 924–927.
DAC-2004-Pomeranz #functional #generative #on the #testing: On the generation of scan-based test sets with reachable states for testing under functional operation conditions (IP), pp. 928–933.
DAC-2004-WohlWP #architecture #scalability: Scalable selector architecture for x-tolerant deterministic BIST (PW, JAW, SP), pp. 934–939.
DAC-2004-Pomeranz04a: Scan-BIST based on transition probabilities (IP), pp. 940–943.
DAC-2004-SunKV #taxonomy #testing: Combining dictionary coding and LFSR reseeding for test data compression (XS, LLK, BV), pp. 944–947.
DAC-2004-VuleticPI #configuration management #memory management: Virtual memory window for application-specific reconfigurable coprocessors (MV, LP, PI), pp. 948–953.
DAC-2004-LyseckyVT #compilation: Dynamic FPGA routing for just-in-time FPGA compilation (RLL, FV, SXDT), pp. 954–959.
DAC-2004-HandaV #algorithm #online #performance: An efficient algorithm for finding empty space for online FPGA placement (MH, RV), pp. 960–965.

Sharad Malik, Limor Fix, Andrew B. KahngProceedings of the 41st Design Automation ConferenceDAC, 2004.

Contents (197 items)

Sharad Malik, Limor Fix, Andrew B. Kahng
Proceedings of the 41st Design Automation Conference
DAC, 2004.