Travelled to:1 × France
Collaborated with:D.Rossi M.Spica C.Metra
Talks about:reliabl (1) perform (1) correct (1) analysi (1) memori (1) error (1) high (1) code (1) cach (1)
Person: N. Timoncini
DBLP: Timoncini:N=
Contributed to:
2011Wrote 1 papers:
- DATE-2011-RossiTSM #analysis #fault #memory management #performance #reliability
- Error correcting code analysis for cache memory high reliability and performance (DR, NT, MS, CM), pp. 1620–1625.