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Travelled to:
2 × USA
Collaborated with:
M.Dagenais S.Gaiotti V.K.Agarwal
Talks about:
transistor (1) worst (1) minim (1) logic (1) group (1) estim (1) delay (1) case (1) bool (1)

Person: Nicholas C. Rumin

DBLP DBLP: Rumin:Nicholas_C=

Contributed to:

DAC 19891989
DAC 19851985

Wrote 2 papers:

DAC-1989-GaiottiDR #estimation #worst-case
Worst-case Delay Estimation of Transistor Groups (SG, MD, NCR), pp. 491–495.
DAC-1985-DagenaisAR #logic
The McBOOLE logic minimizer (MD, VKA, NCR), pp. 667–673.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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