BibSLEIGH — Proceedings of the 26th Design Automation Conference

Donald E. Thomas
Proceedings of the 26th Design Automation Conference
DAC, 1989.

SYS

@proceedings{DAC-1989,
	acmid         = "74382",
	address       = "Las Vegas, Nevada, USA",
	editor        = "Donald E. Thomas",
	publisher     = "{ACM Press}",
	title         = "{Proceedings of the 26th Design Automation Conference}",
	year          = 1989,
}

Contents (157 items)

DAC-1989-PaulinK #algorithm #scheduling #synthesis: Scheduling and Binding Algorithms for High-Level Synthesis (PGP, JPK), pp. 1–6.
DAC-1989-PotkonjackR #algorithm #graph #resource management #scheduling: A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs (MP, JMR), pp. 7–12.
DAC-1989-SadayappanV #matrix #performance #simulation: Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers (PS, VV), pp. 13–18.
DAC-1989-NgV #framework #multi #scheduling #simulation: A Framework for Scheduling Multi-Rate Circuit Simulation (APCN, VV), pp. 19–24.
DAC-1989-OdentCM #feedback #implementation #multi #scalability: Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator (PO, LJMC, HDM), pp. 25–30.
DAC-1989-AdamsS #generative #layout: Template Style Considerations for Sea-of-Gates Layout Generation (GDA, CHS), pp. 31–36.
DAC-1989-LinDY #2d #layout #matrix #synthesis: Gate Matrix Layout Synthesis with Two-Dimensional Folding (IL, DHCD, SHCY), pp. 37–42.
DAC-1989-Marple #layout #optimisation: Transistor Size Optimization in the Tailor Layout System (DM), pp. 43–48.
DAC-1989-Karatsu #design #standard: VLSI Design Language Standardization Effort in Japan (OK), pp. 50–55.
DAC-1989-JainKMP #experience #synthesis: Experience with ADAM Synthesis System (RJ, KK, MJM, ACP), pp. 56–61.
DAC-1989-LagneseT #architecture #clustering #design: Architectural Partitioning for System Level Design (EDL, DET), pp. 62–67.
DAC-1989-BalakrishnanM #approach #design #scheduling #synthesis: Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration (MB, PM), pp. 68–74.
DAC-1989-HayatiP #automation #behaviour #specification: Automatic Production of Controller Specifications from Control and Timing Behavioral Descriptions (SH, AP), pp. 75–80.
DAC-1989-SouleG #distributed #logic #parallel #simulation: Characterization of Parallelism and Deadlocks in Distributed Digital Logic Simulation (LS, AG), pp. 81–86.
DAC-1989-WangM #functional #scheduling #simulation: Scheduling High-Level Blocks for Functional Simulation (ZW, PMM), pp. 87–90.
DAC-1989-KravitzBR #parallel #simulation: Massively Parallel Switch-Level Simulation: A Feasibility Study (SAK, REB, RAR), pp. 91–97.
DAC-1989-ChungC #parallel #simulation #using: Data Parallel Simulation Using Time-Warp on the Connection Machine (MJC, YC), pp. 98–103.
DAC-1989-TrickD #behaviour #layout #named #synthesis #tool support: LASSIE: Structure to Layout for Behavioral Synthesis Tools (MTT, SWD), pp. 104–109.
DAC-1989-LukD #layout #multi #optimisation: Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout (WKL, AAD), pp. 110–115.
DAC-1989-LokanathanK #graph #performance: Performance optimized floor planning by graph planarization (BL, EK), pp. 116–121.
DAC-1989-IgusaBS: ORCA a Sea-of-Gates Place and Route System (MI, MB, ALSV), pp. 122–127.
DAC-1989-McFarland #social: The Social Implications of Computerization: Making the Technology Humane (MCM), pp. 129–134.
DAC-1989-BirminghamGS #design: The MICON System for Computer Design (WPB, APG, DPS), pp. 135–140.
DAC-1989-LeeGHHBBG #design #named #programmable: GABRIEL: A Design Environment for Programmable DSPs (EAL, EG, HH, WHH, SSB, JCB, EG), pp. 141–146.
DAC-1989-KumarKKG #automation #behaviour #synthesis: Automatic Synthesis of Microprogrammed Control Units from Behavioral Descriptions (AK, SK, PK, SG), pp. 147–154.
DAC-1989-Groenveld #on the: On Global Wire Ordering for Macro-Cell Routing (PG), pp. 155–160.
DAC-1989-HoVW #approach #problem: A New Approach to the Rectilinear Steiner Tree Problem (JMH, GV, CKW), pp. 161–166.
DAC-1989-SherwaniD #heuristic #problem: A New Heuristic for Single Row Routing Problems (NAS, JSD), pp. 167–172.
DAC-1989-SalzH #incremental #named: IRSIM: An Incremental MOS Switch-Level Simulator (AS, MH), pp. 173–178.
DAC-1989-BlaauwSMAR #automation #behaviour #generative #modelling: Automatic Generation of Behavioral Models from Switch-Level Descriptions (DB, DGS, RBMT, JAA, JTR), pp. 179–184.
DAC-1989-Tamura #fault #functional #logic: Locating Functional Errors in Logic Circuits (KAT), pp. 185–191.
DAC-1989-Wasserman #automation #design: CASE Environments for Design Automation (AIW), pp. 193–196.
DAC-1989-DaniellD #approach #design #framework #object-oriented: An Object Oriented Approach to CAD Tool Control within a Design Framework (JD, SWD), pp. 197–202.
DAC-1989-FrydmanGGB #named: DeBuMA: Description, Building and Management of Applications (CSF, NG, MG, PB), pp. 203–208.
DAC-1989-VanHornR #architecture #automation #design #experience #framework: Experience with D-BUS Architecture for a Design Automation Framework (ECV, RRR), pp. 209–214.
DAC-1989-HwangOI #communication #complexity #logic #multi #synthesis #using: Multi-Level Logic Synthesis Using Communication Complexity (TH, RMO, MJI), pp. 215–220.
DAC-1989-McGeerB #logic #performance: Efficient Prime Factorization of Logic Expressions (PCM, RKB), pp. 221–225.
DAC-1989-Coppola #algorithm #analysis #logic: New Methods in the Analysis of Logic Minimization Data and Algorithms (AJC), pp. 226–231.
DAC-1989-ChenC #automation #layout: The Layout Synthesizer: An Automatic Netlist-to-Layout System (CCC, SLC), pp. 232–238.
DAC-1989-OngLL #automation #named #synthesis: GENAC: An Automatic Cell Synthesis Tool (CLO, JTL, CYL), pp. 239–244.
DAC-1989-Al-KhaliliZA #generative: A Module Generator for Optimized CMOS Buffers (AJAK, YZ, DAK), pp. 245–250.
DAC-1989-WinslettKHW #coordination #design #using: Use of Change Coordination in an Information-rich Design Environment (MW, DWK, KH, GW), pp. 252–257.
DAC-1989-Biliris #database #design #evolution: Database Support for Evolving Design Objects (AB), pp. 258–263.
DAC-1989-SilvaGKN #version control: Protection and Versioning for OCT (MJS, DG, RHK, RN), pp. 264–269.
DAC-1989-Devadas #logic #multi #synthesis: Approaches to Multi-level Sequential Logic Synthesis (SD), pp. 270–276.
DAC-1989-SaldanhaWBS #logic #multi #using: Multi-level Logic Simplification Using Don’t Cares and Filters (AS, ARW, RKB, ALSV), pp. 277–282.
DAC-1989-GoreR #array #automation #equation #logic #programmable #synthesis #using: Automatic Synthesis of Boolean Equations Using Programmable Array Logic (RG, KR), pp. 283–289.
DAC-1989-ShinL #2d #algorithm #layout #performance: An Efficient Two-Dimensional Layout Compaction Algorithm (HS, CYL), pp. 290–295.
DAC-1989-WaterkampWBRS #layout: Technology Tracking of Non Manhattan VLSI Layout (JW, RW, RB, MR, GS), pp. 296–301.
DAC-1989-Lo #automation #generative #layout: Automatic Tub Region Generation for Symbolic Layout Compaction (CYL), pp. 302–306.
DAC-1989-Keutzer #architecture #design #generative #logic #synthesis: Three Competing Design Methodologies for ASIC’s: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation (KK), pp. 308–313.
DAC-1989-Devadas89a #composition: General Decomposition of Sequential Machines: Relationships to State Assignment (SD), pp. 314–320.
DAC-1989-SaucierDP #using: State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory (GS, CD, FP), pp. 321–326.
DAC-1989-VillaS #finite #implementation #logic #named #state machine: NOVA: State Assignment of Finite State Machines for Optimal Two-level Logic Implementations (TV, ALSV), pp. 327–332.
DAC-1989-Paulin #clustering #finite #state machine: Horizontal Partitioning of PLA-based Finite State Machines (PGP), pp. 333–338.
DAC-1989-PatilB #algorithm #bound #branch #generative #parallel #testing: A Parallel Branch and Bound Algorithm for Test Generation (SP, PB), pp. 339–343.
DAC-1989-LeeHK #fault #generative #testing #using: Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits (HKL, DSH, KK), pp. 345–350.
DAC-1989-GloverM #approach #fault #testing: A Deterministic Approach to Adjacency Testing for Delay Faults (CTG, MRM), pp. 351–356.
DAC-1989-SchulzFF #fault #parallel #simulation: Parallel Pattern Fault Simulation of Path Delay Faults (MHS, FF, KF), pp. 357–363.
DAC-1989-PrasitjutrakulK #approach #programming: Path-Delay Constrained Floorplanning: A Mathematical Programming Approach for Initial Placement (SP, WJK), pp. 364–369.
DAC-1989-JacksonK: Performance-driven Placement of Cell Based IC’s (MABJ, ESK), pp. 370–375.
DAC-1989-HerrigelF #optimisation: An Analytic Optimization Technique for Placement of Macro-Cells (AH, WF), pp. 376–381.
DAC-1989-SastryP #clustering #problem #statistics: An Investigation into Statistical Properties of Partitioning and Floorplanning Problems (SS, JIP), pp. 382–387.
DAC-1989-BruceMH #multi: Multi Chip Modules (RHB, WPM, JH), pp. 389–393.
DAC-1989-PreasPC #automation #hybrid #layout: Automatic Layout of Silicon-on-Silicon Hybrid Packages (BP, MP, DC), pp. 394–399.
DAC-1989-Libeskind-HadasL #network #problem: Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks (RLH, CLL), pp. 400–405.
DAC-1989-YihM #clustering #design #network: A Neural Network Design for Circuit Partitioning (JSY, PM), pp. 406–411.
DAC-1989-Yu #case study: A Study of the Applicability of Hopfield Decision Neural Nets to VLSI CAD (MLY), pp. 412–417.
DAC-1989-ChoB #fault #generative #simulation: Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation (KC, REB), pp. 418–423.
DAC-1989-ChengY #difference #fault #memory management #performance #simulation #using: Differential Fault Simulation — a Fast Method Using Minimal Memory (WTC, MLY), pp. 424–428.
DAC-1989-Norrod #algorithm #automation #generative #hardware #testing: An Automatic Test Generation Algorithm for Hardware Description Languages (FEN), pp. 429–434.
DAC-1989-LiawTL #named #verification: VVDS: A Verification/Diagnosis System for VHDL (HTL, KTT, CSL), pp. 435–440.
DAC-1989-NowakM #code generation #hardware #verification: Verification of Hardware Descriptions by Retargetable Code Generation (LN, PM), pp. 441–447.
DAC-1989-BamjiA #grammarware #named #parsing: GRASP: A Grammar-based Schematic Parser (CB, JA), pp. 448–453.
DAC-1989-Strojwas #design: Design for Manufacturability and Yield (AJS), pp. 454–459.
DAC-1989-HungRH #flexibility #named: MIOS: A Flexible System for PCB Manufacturing (ACH, PMR, PJH), pp. 460–465.
DAC-1989-SmithDDCHJd #development: FACE Core Environment: The Model and Its Application in CAE/CAD Tool Development (WDS, DAD, MD, JC, MJH, JRJ, MAd), pp. 466–471.
DAC-1989-Muller-GlaserB #approach #design #specification #using: An Approach to Intelligent Assistance for the Specification of ASIC Design Using Objects and Rules (KDMG, JB), pp. 472–477.
DAC-1989-AudeK #adaptation #design #representation #using: Representation and Use of Design Rules within a Technology Adaptable CAD System (JSA, HJK), pp. 478–484.
DAC-1989-CahnK #clustering #network: Computing Signal Delay in General RC Networks by Tree/Link Partitioning (PKC, KK), pp. 485–490.
DAC-1989-GaiottiDR #estimation #worst-case: Worst-case Delay Estimation of Transistor Groups (SG, MD, NCR), pp. 491–495.
DAC-1989-IshiuraTY #behaviour #logic #simulation #verification: Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits (NI, MT, SY), pp. 497–502.
DAC-1989-BonapaceL #algorithm #design: An O(nlogm) Algorithm for VLSI Design Rule Checking (CRB, CYL), pp. 503–507.
DAC-1989-HedenstiernaJ #design #layout #using: The Use of Inverse Layout Trees for Hierarchical Design Rule Checking (NH, KOJ), pp. 508–512.
DAC-1989-BolsensRCM #analysis #behaviour #debugging #logic: Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour (IB, WDR, LJMC, HDM), pp. 513–518.
DAC-1989-OgiharaMYM #effectiveness #generative #named #reliability #testing: MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits (TO, KM, GY, SM), pp. 519–524.
DAC-1989-JoneP #approach #clustering #coordination #generative #pseudo #testing: A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing (WBJ, CAP), pp. 525–534.
DAC-1989-JonePP #concurrent #testing: A Scheme for Overlaying Concurrent Testing of VLSI Circuits (WBJ, CAP, MP), pp. 531–536.
DAC-1989-BusetE #architecture #interface #named #synthesis #visual notation: ACE: A Hierarchical Graphical Interface for Architectual Synthesis (OAB, MIE), pp. 537–542.
DAC-1989-SetliffR #automation #named #physics #synthesis: ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software (DES, RAR), pp. 543–548.
DAC-1989-DragomireckyGJDSd #synthesis #user interface #visual notation: High-Level Graphical User Interface Management in the FACE Synthesis Environment (MD, EPG, JRJ, DAD, WDS, MAd), pp. 549–554.
DAC-1989-DuYG #analysis #on the #problem: On the General False Path Problem in Timing Analysis (DHCD, SHY, SG), pp. 555–560.
DAC-1989-McGeerB89a #algorithm #network #performance: Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network (PCM, RKB), pp. 561–567.
DAC-1989-PerremansCM #analysis: Static Timing Analysis of Dynamically Sensitizable Paths (SP, LJMC, HDM), pp. 568–573.
DAC-1989-GuraA: Average Interconnection Length and Interconnection Distribution Based on Rent’s Rule (CVG, JAA), pp. 574–577.
DAC-1989-ZhangPR #performance: Efficient Final Placement Based on Nets-as-Points (XZ, LTP, RAR), pp. 578–581.
DAC-1989-JabriS #algorithm #knowledge-based #named #top-down: PIAF: A Knowledge-based/Algorithm Top-Down Floorplanning System (MAJ, DJS), pp. 582–585.
DAC-1989-WongS #optimisation #performance: Efficient Floorplan Area Optimization (DFW, PSS), pp. 586–589.
DAC-1989-SargentB #algorithm #fault #parallel #standard: A Parallel Row-based Algorithm for Standard Cell Placement with Integrated Error Control (JSS, PB), pp. 590–593.
DAC-1989-GabbeS #clustering: A Note on Clustering Modules for Floorplanning (JDG, PAS), pp. 594–597.
DAC-1989-Knapp #interactive #optimisation: An Interactive Tool for Register-level Structure Optimization (DK), pp. 598–601.
DAC-1989-WooS #adaptation #functional: A Technology-adaptive Allocation of Functional Units and Connections (NSW, HS), pp. 602–605.
DAC-1989-LisG #modelling #synthesis #using: VHDL Synthesis Using Structured Modeling (JL, DG), pp. 606–609.
DAC-1989-BirminghamS #design: Capturing Designer Expertise the CGEN System (WPB, DPS), pp. 610–613.
DAC-1989-HwangWF #architecture #configuration management #evaluation #using: Evaluation of a Reconfigurable Architecture for Digital Beamforming Using the OODRA Workbench (DLH, TLW, WKF), pp. 614–617.
DAC-1989-RumseyS #simulation: An ASIC Methodology for Mixed Analog-Digital Simulation (MR, JS), pp. 618–621.
DAC-1989-MilsomSCMAS #layout #named #simulation: FACET: A CAE System for RF Analogue Simulation Including Layout (RFM, KJS, SGC, JCM, SA, FNS), pp. 622–625.
DAC-1989-YuZYL #algorithm #behaviour #convergence #novel: A Novel Algorithm for Improving Convergence Behavior of Circuit Simulators (ZY, WZ, ZY, YEL), pp. 626–629.
DAC-1989-YangK #development #named #novel #simulation: iSMILE: A Novel Circuit Simulation Program with Emphasis on New Device Model Development (ATY, SMK), pp. 630–633.
DAC-1989-PillageHR #analysis #evaluation #named: AWEsim: Asymptotic Waveform Evaluation for Timing Analysis (LTP, XH, RAR), pp. 634–637.
DAC-1989-RoyA #approach #novel #using #verification: A Novel Approach to Accurate Timing Verification Using RTL Descriptions (KR, JAA), pp. 638–641.
DAC-1989-George #hardware #modelling #simulation: Evaluating Hardware Models in DIGITAL’s System Simulation Environment (AKG), pp. 642–644.
DAC-1989-AgrawalTD #algorithm #hardware #logic: Algorithms for Accuracy Enhancement in a Hardware Logic Simulator (PA, RT, WJD), pp. 645–648.
DAC-1989-YenDG #algorithm #analysis #performance: Efficient Algorithms for Extracting the K most Critical Paths in Timing Analysis (SHY, DHCD, SG), pp. 649–654.
DAC-1989-WeinerS #analysis #logic #synthesis: Timing Analysis in a Logic Synthesis Environment (NW, ALSV), pp. 655–661.
DAC-1989-WeninVCLG #layout #rule-based #verification: Rule-based VLSI Verification System Constrained by Layout Parasitics (JW, JV, MVC, JL, PG), pp. 662–667.
DAC-1989-BenkoskiS #interactive #modelling #multi #verification: Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator (JB, AJS), pp. 668–673.
DAC-1989-BhatN #architecture: Special Purpose Architecture for Accelerating Bitmap DRC (NBB, SKN), pp. 674–677.
DAC-1989-MeijsG #finite #performance: An Efficient Finite Element Method for Submicron IC Capacitance Extraction (NPvdM, AJvG), pp. 678–681.
DAC-1989-Chiang #question: Resistance Extraction and Resistance Calculation in GOALIE? (KWC), pp. 682–685.
DAC-1989-StokK #network: From Network to Artwork (LS, GPK), pp. 686–689.
DAC-1989-LueM: Extracting Schematic-like Information from CMOS Circuit Net-lists (WJL, LPM), pp. 690–693.
DAC-1989-VandweerdCRSM #automation #generative #named: REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures (IV, KC, LR, PS, HDM), pp. 694–697.
DAC-1989-IrwinO #2d #comparison #layout #matrix #tool support: A Comparison of Four Two-dimensional Gate Matrix Layout Tools (MJI, RMO), pp. 698–701.
DAC-1989-JustSK #named: Plowing: Modifying Cells and Routing 45: 9D — Layouts (KMJ, WLS, TK), pp. 702–705.
DAC-1989-Ghewala #named #testing: CrossCheck: A Cell Based VLSI Testability Solution (TG), pp. 706–709.
DAC-1989-HemmadyR #on the: On the Repair of Redundant RAMs (VGH, SMR), pp. 710–713.
DAC-1989-RajsumanJM #detection #fault #using: CMOS Stuck-open Fault Detection Using Single Test Patterns (RR, APJ, YKM), pp. 714–717.
DAC-1989-DervisogluK #debugging #named #state of the art #tool support: ATLAS/ELA: Scan-based Software Tools for Reducing System Debug Time in a State-of-the-art Workstation (BID, MAK), pp. 718–721.
DAC-1989-DaveP #generative #testing #using: A Functional-Level Test Generation Methodology Using Two-level Representations (UJD, JHP), pp. 722–725.
DAC-1989-WangKL #approach #fault #logic #robust #set: A New Approach to Derive Robust Sets for Stuck-open Faults in CMOS Combinational Logic Circuits (JFW, TYK, JYL), pp. 726–729.
DAC-1989-MaoC #fault #testing: A Simplified Six-waveform Type Method for Delay Fault Testing (WM, MDC), pp. 730–733.
DAC-1989-NarayananP #algorithm #fault #parallel #simulation: A Massively Parallel Algorithm for Fault Simulation on the Connection Machine (VN, VP), pp. 734–737.
DAC-1989-HoevenLDD #network #simulation: A New Model for the High Level Description and Simulation of VLSI Networks (AJvdH, AAdL, EFD, PD), pp. 738–741.
DAC-1989-Cyre #synthesis #towards: Toward Synthesis from English Descriptions (WRC), pp. 742–745.
DAC-1989-Leung #behaviour #modelling: Behavioral Modeling of Transmission Gates in VHDL (SSL), pp. 746–749.
DAC-1989-JordanW #composition #named: COMP: A VHDL Composition System (PRJ, RDW), pp. 750–753.
DAC-1989-DuttG #behaviour #design #synthesis: Designer Controlled Behavioral Synthesis (NDD, DG), pp. 754–757.
DAC-1989-Blanks #clustering #probability: Partitioning by Probability Condensation (JB), pp. 758–761.
DAC-1989-Kahng #performance: Fast Hypergraph Partition (ABK), pp. 762–766.
DAC-1989-SaabR #approach #clustering: An Evolution-Based Approach to Partitioning ASIC Systems (YS, VBR), pp. 767–770.
DAC-1989-Vijayan #clustering: Min-cost Partitioning on a Tree Structure and Applications (GV), pp. 771–774.
DAC-1989-BuiHJL #algorithm #graph #performance: Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms (TNB, CH, CJ, FTL), pp. 775–778.
DAC-1989-GangulyP: Compaction of a Routed Channel on the Connection Machine (SG, VP), pp. 779–782.
DAC-1989-DuttaM #automation #network: Automatic Sizing of Power/Ground (P/G) Networks in VLSI (RD, MMS), pp. 783–786.
DAC-1989-Chowdhury #design #graph #network #reliability: Optimum Design of Reliable IC Power Networks Having General Graph Topologies (SC), pp. 787–790.
DAC-1989-FujiharaSIY #automation #named #optimisation #performance: DYNAJUST: An Efficient Automatic Routing Technique Optimizing Delay Conditions (YF, YS, YI, MY), pp. 791–794.
DAC-1989-PitaksanonkulTLG #algorithm #named: DTR: A Defect-Tolerant Routing Algorithm (AP, ST, CL, JAG), pp. 795–798.
DAC-1989-TheWC #layout: VIA Minimization by Layout Modification (KST, DFW, JC), pp. 799–802.
DAC-1989-LiS: A Unified Data Exchange Environment Based on EDIF (WL, HS), pp. 803–806.
DAC-1989-MillerGSW #design #integration #object-oriented: The Object-Oriented Integration Methodology of the Cadlab Work Station Design Environment (JM, KG, GS, CW), pp. 807–810.
DAC-1989-KollaritschLMSS #design #representation: A Unified Design Representation Can Work (PK, SL, DM, DS, PS), pp. 811–813.
DAC-1989-SiepmannZ #design #object-oriented: An Object-Oriented Datamodel for the VLSI Design System PLAYOUT (ES, GZ), pp. 814–817.
DAC-1989-Roberts #data-driven #named: CEDIF: A Data Driven EDIF Reader (MR), pp. 818–821.
DAC-1989-Jones #compilation #online #performance: Fast Online/Offline Netlist Compilation of Hierarchical Schematics (LGJ), pp. 822–825.
DAC-1989-GoossensVM #optimisation #scheduling: Loop Optimization in Register-Transfer Scheduling for DSP-Systems (GG, JV, HDM), pp. 826–831.
DAC-1989-YasuuraI #design #hardware #semantics #standard: Semantics of a Hardware Design Language for Japanese Standardization (HY, NI), pp. 836–839.

Donald E. ThomasProceedings of the 26th Design Automation ConferenceDAC, 1989.

Contents (157 items)

Donald E. Thomas
Proceedings of the 26th Design Automation Conference
DAC, 1989.