BibSLEIGH
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Travelled to:
1 × France
Collaborated with:
N.Banerjee K.S.Chatha
Talks about:
architectur (1) perform (1) network (1) power (1) model (1) chip (1)

Person: Praveen Vellanki

DBLP DBLP: Vellanki:Praveen

Contributed to:

DATE v2 20042004

Wrote 1 papers:

DATE-v2-2004-BanerjeeVC #architecture #performance
A Power and Performance Model for Network-on-Chip Architectures (NB, PV, KSC), pp. 1250–1255.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.