Travelled to:2 × Germany
3 × France
5 × USA
Collaborated with:W.Che C.Ostler V.Hanumaiah S.B.K.Vrudhula S.Zhang K.Srinivasan G.Leary A.Panda N.Banerjee P.Vellanki R.Rao
Talks about:processor (8) architectur (5) network (4) stream (4) multicor (3) thermal (3) system (3) memori (3) multi (3) embed (3)
Person: Karam S. Chatha
DBLP: Chatha:Karam_S=
Contributed to:
201220112010
2010200920092007200720062004Wrote 11 papers:
- DAC-2012-CheC #embedded #manycore
- Unrolling and retiming of stream applications onto embedded multicore processors (WC, KSC), pp. 1272–1277.
- DAC-2012-LearyCC #architecture #memory management #synthesis
- System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC (GL, WC, KSC), pp. 672–677.
- DAC-2011-CheC #compilation #embedded #manycore #memory management #source code
- Compilation of stream programs onto scratchpad memory based embedded multicore processors through retiming (WC, KSC), pp. 122–127.
- DAC-2010-ZhangC #embedded
- Thermal aware task sequencing on embedded processors (SZ, KSC), pp. 585–590.
- DATE-2010-ChePC #compilation #manycore #source code
- Compilation of stream programs for multicore processors that incorporate scratchpad memories (WC, AP, KSC), pp. 1118–1123.
- DAC-2009-HanumaiahRVC #constraints #manycore #throughput
- Throughput optimal task allocation under thermal constraints for multi-core processors (VH, RR, SBKV, KSC), pp. 776–781.
- DATE-2009-HanumaiahVC #constraints #manycore #performance
- Performance optimal speed control of multi-core processors under thermal constraints (VH, SBKV, KSC), pp. 1548–1551.
- DAC-2007-OstlerC #algorithm #approximate #architecture #concurrent #multi #network #thread
- Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures (CO, KSC), pp. 801–804.
- DATE-2007-OstlerC #architecture #network
- An ILP formulation for system-level application mapping on network processor architectures (CO, KSC), pp. 99–104.
- DATE-2006-SrinivasanC #architecture #complexity #design #heuristic
- A low complexity heuristic for design of custom network-on-chip architectures (KS, KSC), pp. 130–135.
- DATE-v2-2004-BanerjeeVC #architecture #performance
- A Power and Performance Model for Network-on-Chip Architectures (NB, PV, KSC), pp. 1250–1255.