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Travelled to:
2 × USA
Collaborated with:
J.Monaco D.Holloway R.Bailey C.Njinda R.F.Molyneaux C.Beh
Talks about:
microprocessor (1) methodolog (1) function (1) regener (1) circuit (1) effici (1) design (1) verif (1) power (1) clock (1)

Person: Rajesh Raina

DBLP DBLP: Raina:Rajesh

Contributed to:

DAC 19971997
DAC 19961996

Wrote 2 papers:

DAC-1997-RainaBNMB #design #performance #testing
Efficient Testing of Clock Regenerator Circuits in Scan Designs (RR, RB, CN, RFM, CB), pp. 95–100.
DAC-1996-MonacoHR #functional #verification
Functional Verification Methodology for the PowerPC 604 Microprocessor (JM, DH, RR), pp. 319–324.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.