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Travelled to:
1 × France
2 × Germany
Collaborated with:
K.Weinberger S.Bulach C.Stolte G.Stoll M.Rosenblum P.Hanrahan P.v.Staa H.Heidbrink B.Potock J.Mueller W.Kisselmann W.Herden
Talks about:
design (2) workflow (1) parallel (1) electron (1) process (1) perform (1) creativ (1) circuit (1) analysi (1) acceler (1)

Person: Robert Bosch

DBLP DBLP: Bosch:Robert

Contributed to:

DATE 20082008
DATE 20012001
HPCA 20002000

Wrote 3 papers:

DATE-2008-WeinbergerBB #design #modelling #petri net #process #verification #workflow
Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits (KW, SB, RB), pp. 937–938.
DATE-2001-StaaBHPMKH #data transformation #design
Data management: limiter or accelerator for electronic design creativity (PvS, RB, HH, BP, JM, WK, WH), pp. 162–163.
HPCA-2000-BoschSSRH #analysis #case study #parallel #performance #using #visualisation
Performance Analysis and Visualization of Parallel Systems Using SimOS and Rivet: A Case Study (RB, CS, GS, MR, PH), pp. 360–371.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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