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Travelled to:
1 × USA
Collaborated with:
L.Chen L.Zhao T.M.Pinkston
Talks about:
perform (1) penalti (1) network (1) power (1) minim (1) gate (1) clos (1) chip (1)

Person: Ruisheng Wang

DBLP DBLP: Wang:Ruisheng

Contributed to:

HPCA 20142014

Wrote 1 papers:

HPCA-2014-ChenZWP #named #performance
MP3: Minimizing performance penalty for power-gating of Clos network-on-chip (LC, LZ, RW, TMP), pp. 296–307.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.