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Travelled to:
1 × Germany
1 × USA
Collaborated with:
C.Li L.P.Carloni S.Ramesh V.D'Silva N.Chandra B.Vijayalakshmi
Talks about:
floorplan (1) structur (1) toolset (1) exploit (1) system (1) verif (1) optim (1) multi (1) model (1) logic (1)

Person: Sampada Sonalkar

DBLP DBLP: Sonalkar:Sampada

Contributed to:

DATE 20102010
CAV 20042004

Wrote 2 papers:

DATE-2010-LiSC #logic #manycore
Exploiting local logic structures to optimize multi-core SoC floorplanning (CHL, SS, LPC), pp. 1291–1296.
CAV-2004-RameshSDCV #modelling #tool support #verification
A Toolset for Modelling and Verification of GALS Systems (SR, SS, VD, NC, BV), pp. 506–509.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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