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Travelled to:
2 × USA
Collaborated with:
S.S.Sapatnekar C.V.Kashyap C.H.Kim
Talks about:
framework (1) synthesi (1) circuit (1) analysi (1) sensit (1) digit (1) block (1) time (1) nbti (1) base (1)

Person: Sanjay V. Kumar

DBLP DBLP: Kumar:Sanjay_V=

Contributed to:

DAC 20082008
DAC 20072007

Wrote 2 papers:

DAC-2008-KumarKS #analysis #framework
A framework for block-based timing sensitivity analysis (SVK, CVK, SSS), pp. 688–693.
DAC-2007-KumarKS #synthesis
NBTI-Aware Synthesis of Digital Circuits (SVK, CHK, SSS), pp. 370–375.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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