BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × Germany
3 × USA
Collaborated with:
V.Suthar H.Arslan K.Zhong W.Deng V.Verma
Talks about:
effici (3) satisfact (2) provabl (2) multipl (2) circuit (2) fpgas (2) vlsi (2) test (2) line (2) interconnect (1)

Person: Shantanu Dutt

DBLP DBLP: Dutt:Shantanu

Contributed to:

DATE 20062006
DAC 20042004
DAC 20022002
DAC 19961996

Wrote 5 papers:

DATE-2006-DuttA #incremental #locality #performance #using
Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations (SD, HA), pp. 768–773.
DATE-2006-SutharD #detection #fault #multi #online #performance #testing
Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults (VS, SD), pp. 1165–1170.
DAC-2004-VermaDS #online #performance #testing
Efficient on-line testing of FPGAs with provable diagnosabilities (VV, SD, VS), pp. 498–503.
DAC-2002-ZhongD #algorithm #constraints #multi #optimisation
Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control (KZ, SD), pp. 854–859.
DAC-1996-DuttD #approach #clustering
A Probability-Based Approach to VLSI Circuit Partitioning (SD, WD), pp. 100–105.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.