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Travelled to:
1 × USA
Collaborated with:
K.Yoshida T.Mitsuhashi Y.Nakada T.Chiba K.Ogita
Talks about:
circuit (1) system (1) layout (1) integr (1) scale (1) check (1) larg (1)

Person: Shinji Nakatsuka

DBLP DBLP: Nakatsuka:Shinji

Contributed to:

DAC 19771977

Wrote 1 papers:

DAC-1977-YoshidaMNCON #layout #scalability
A layout checking system for large scale integrated circuits (KY, TM, YN, TC, KO, SN), pp. 322–330.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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