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Travelled to:
1 × USA
Collaborated with:
H.R.Ghasemi N.S.Kim
Talks about:
architectur (1) processor (1) heterogen (1) perform (1) voltag (1) size (1) high (1) chip (1) cell (1) cach (1)

Person: Stark C. Draper

DBLP DBLP: Draper:Stark_C=

Contributed to:

HPCA 20112011

Wrote 1 papers:

HPCA-2011-GhasemiDK #architecture #using
Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors (HRG, SCD, NSK), pp. 38–49.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.