BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × USA
Collaborated with:
Y.Massoud S.S.Majors J.White
Talks about:
interconnect (1) techniqu (1) layout (1) induct (1) minim (1) self (1) chip (1)

Person: Tareq Bustami

DBLP DBLP: Bustami:Tareq

Contributed to:

DAC 19981998

Wrote 1 papers:

DAC-1998-MassoudMBW #layout
Layout Techniques for Minimizing On-Chip Interconnect Self Inductance (YM, SSM, TB, JW), pp. 566–571.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.