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Travelled to:
1 × USA
Collaborated with:
S.L.Sam D.S.Boning A.Chandrakasan R.Vallishayee S.R.Nassif
Talks about:
interconnect (1) methodolog (1) systemat (1) perform (1) circuit (1) within (1) variat (1) effect (1) model (1) devic (1)

Person: Vikas Mehrotra

DBLP DBLP: Mehrotra:Vikas

Contributed to:

DAC 20002000

Wrote 1 papers:

DAC-2000-MehrotraSBCVN #modelling #performance
A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance (VM, SLS, DSB, AC, RV, SRN), pp. 172–175.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.