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Travelled to:
2 × USA
Collaborated with:
N.Ahmed M.Tehranipoor
Talks about:
delay (3) test (2) transit (1) pattern (1) generat (1) voltag (1) suppli (1) screen (1) design (1) defect (1)

Person: Vinay Jayaram

DBLP DBLP: Jayaram:Vinay

Contributed to:

DAC 20072007
DAC 20062006

Wrote 2 papers:

DAC-2007-AhmedTJ #design #fault #generative
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design (NA, MT, VJ), pp. 533–538.
DAC-2006-AhmedTJ #fault
Timing-based delay test for screening small delay defects (NA, MT, VJ), pp. 320–325.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.