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Travelled to:
1 × France
1 × USA
1 × United Kingdom
2 × Germany
Collaborated with:
Y.Tan B.S.Akgul T.Akgul S.Pande
Talks about:
cach (3) analysi (2) system (2) time (2) uniprocessor (1) processor (1) preemptiv (1) synchron (1) parametr (1) support (1)

Person: Vincent John Mooney III

DBLP DBLP: III:Vincent_John_Mooney

Contributed to:

LCTES 20052005
DATE v2 20042004
ICSE 20042004
DATE 20032003
DATE 20012001

Wrote 5 papers:

LCTES-2005-TanM #analysis
WCRT analysis for a uniprocessor with a unified prioritized cache (YT, VJMI), pp. 175–182.
DATE-v2-2004-TanM #analysis #multi #realtime
Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches (YT, VJMI), pp. 1034–1039.
ICSE-2004-AkgulMP #assembly #execution #performance #slicing
A Fast Assembly Level Reverse Execution Method via Dynamic Slicing (TA, VJMI, SP), pp. 522–531.
DATE-2003-AkgulM #generative #named
PARLAK: Parametrized Lock Cache Generator (BSA, VJMI), pp. 11138–11139.
DATE-2001-AkgulM #hardware
System-on-a-chip processor synchronization support in hardware (BSA, VJMI), pp. 633–641.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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