BibSLEIGH — hardware tag

hardware

hardware

Tag #hardware

671 papers:

ASPLOS-2020-Ainsworth0 #parallel #programmable #security: The Guardian Council: Parallel Programmable Hardware Security (SA, TMJ0), pp. 1277–1293.
ASPLOS-2020-KarandikarOAMKN #co-evolution #design #named #performance #profiling: FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design (SK, AJO, AA, HM, RHK, BN, KA), pp. 715–731.
ASPLOS-2020-Kokologiannakis #memory management #model checking #modelling #named: HMC: Model Checking for Hardware Memory Models (MK, VV), pp. 1157–1171.
ASPLOS-2020-LimN #optimisation #performance #using: Optimizing Nested Virtualization Performance Using Direct Virtual Hardware (JTL, JN), pp. 557–574.
CGO-2020-WangYZM #memory management #performance #scalability #transaction: Efficient and scalable cross-ISA virtualization of hardware transactional memory (WW, PCY, AZ, SM), pp. 107–120.
CoG-2019-RossB #student: Turning the classroom into an escape room with decoder hardware to increase student engagement (RR, CB), pp. 1–4.
KDD-2019-Chellapilla #self: Building a Better Self-Driving Car: Hardware, Software, and Knowledge (KC), p. 3169.
ECOOP-2019-Muijnck-HughesV #interface #type system: A Typing Discipline for Hardware Interfaces (JdMH, WV), p. 27.
POPL-2019-PodkopaevLV #memory management #modelling #programming language: Bridging the gap between programming languages and hardware weak memory models (AP, OL, VV), p. 31.
ASPLOS-2019-KondguliH #named #performance #smt #thread #using: Bootstrapping: Using SMT Hardware to Improve Single-Thread Performance (SK, MH), pp. 687–700.
ASPLOS-2019-LascorzJSPMSNSM #approach #named #network: Bit-Tactical: A Software/Hardware Approach to Exploiting Value and Bit Sparsity in Neural Networks (ADL, PJ, DMS, ZP, MM, SS, MN, KS, AM), pp. 749–763.
ASPLOS-2019-MahmoudVAMMFA #adaptation #fault #named #testing: Minotaur: Adapting Software Testing Techniques for Hardware Errors (AM, RV, KA, SM, DM, CWF, SVA), pp. 1087–1103.
CGO-2019-KimK #generative #using: Translating CUDA to OpenCL for Hardware Generation using Neural Machine Translation (YK, HK), pp. 285–286.
TAP-2019-0002JPW #approximate #question #verification: When Are Software Verification Results Valid for Approximate Hardware? (TI0, MCJ, FP, HW), pp. 3–20.
KDD-2018-SadrediniGBRSW #novel #rule-based #scalability: A Scalable Solution for Rule-Based Part-of-Speech Tagging on Novel Hardware Accelerators (ES, DG, CB, RR, KS, HW), pp. 665–674.
KDD-2018-Smola #algorithm #tool support: Algorithms, Data, Hardware and Tools: A Perfect Storm (AS), p. 2878.
MoDELS-2018-EderBVIK #architecture #automation #deployment #distributed #framework #synthesis: From Deployment to Platform Exploration: Automatic Synthesis of Distributed Automotive Hardware Architectures (JE, AB, SV, AI, MK), pp. 438–446.
OOPSLA-2018-BostonGC #execution #fault tolerance #modelling #named #programmable #verification: Leto: verifying application-specific hardware fault tolerance with programmable execution models (BB, ZG, MC), p. 30.
ASPLOS-2018-CaiRLDWQPW #named #network: VIBNN: Hardware Acceleration of Bayesian Neural Networks (RC, AR, NL0, CD, LW, XQ, MP, YW), pp. 476–488.
ASPLOS-2018-FixNAZQA #parallel #thread #transaction: Hardware Multithreaded Transactions (JF, NPN, SA, HZ, SQ, DIA), pp. 15–29.
ASPLOS-2018-JiZC0 #compilation #network: Bridge the Gap between Neural Networks and Neuromorphic Hardware with a Neural Network Compiler (YJ0, YZ, WC, YX0), pp. 448–460.
ASPLOS-2018-SadrosadatiMESD #named: LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching (MS, AM, SBE, HSA, MD, BF, RA, OM), pp. 489–502.
CGO-2018-SioutasSCBS: Loop transformations leveraging hardware prefetching (SS, SS, HC, TB, LJS), pp. 254–264.
Haskell-2017-AronssonS #co-evolution #design #haskell: Hardware software co-design in Haskell (MA, MS), pp. 162–173.
ICFP-2017-ChoiVSCA #composition #framework #named #parametricity #platform #specification #verification: Kami: a platform for high-level parametric hardware specification and its modular verification (JC, MV, BS, AC, A), p. 30.
ASPLOS-2017-FerraiuoloXZMS #analysis #architecture #data flow #security #verification: Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis (AF, RX, DZ, ACM, GES), pp. 555–568.
ASPLOS-2017-TrippelMLPM #memory management #named #verification: TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA (CT, YAM, DL, MP, MM), pp. 119–133.
CGO-2017-GongCZUK #execution #gpu #kernel #named #scheduling: TwinKernels: an execution model to improve GPU hardware scheduling at compile time (XG, ZC, AKZ, RU, DRK), pp. 39–49.
CGO-2017-SenguptaCBK #bound #memory management #named #transaction #using: Legato: end-to-end bounded region serializability using commodity hardware transactional memory (AS, MC, MDB, MK0), pp. 1–13.
ASPLOS-2016-AsmussenVNHF #co-evolution #design #named: M3: A Hardware/Operating-System Co-Design to Tame Heterogeneous Manycores (NA, MV, BN, HH, GPF), pp. 189–203.
ASPLOS-2016-PrabhakarKBLSKO #configuration management #generative #parallel: Generating Configurable Hardware from Parallel Patterns (RP, DK, KJB, HL, CDS, CK, KO), pp. 651–665.
ASPLOS-2016-ZhangH #comparison #hybrid #performance: Maximizing Performance Under a Power Cap: A Comparison of Hardware, Software, and Hybrid Techniques (HZ, HH), pp. 545–559.
ASPLOS-2016-ZhangLJ #concurrent #detection #memory management #named #performance #transaction #using: TxRace: Efficient Data Race Detection Using Commodity Hardware Transactional Memory (TZ, DL, CJ), pp. 159–173.
TAP-2016-GabmeyerS #graph transformation #lightweight #model checking #off the shelf #verification: Lightweight Symbolic Verification of Graph Transformation Systems with Off-the-Shelf Hardware Model Checkers (SG, MS), pp. 94–111.
VLDB-2015-Ailamaki #database: Databases and Hardware: The Beginning and Sequel of a Beautiful Friendship (AA), pp. 2058–2061.
VLDB-2015-Loaiza #database: Engineering Database Hardware and Software Together (JL), pp. 2052–2063.
VLDB-2015-MakreshanskiLS #memory management #transaction: To Lock, Swap, or Elide: On the Interplay of Hardware Transactional Memory and Lock-Free Indexing (DM, JJL, RS), pp. 1298–1309.
ICSME-2015-Vogel-HeuserFRF #automation #case study #challenge #industrial #maintenance: Challenges for maintenance of PLC-software and its related hardware for automated production systems: Selected industrial Case Studies (BVH, JF, SR, SF, SU), pp. 362–371.
ICSME-2015-WahlerEFP #legacy #manycore #migration: Migrating legacy control software to multi-core hardware (MW, RE, CF, YAP), pp. 458–466.
CIAA-2015-Watson #automaton #finite #implementation #regular expression: Hardware Implementations of Finite Automata and Regular Expressions — Extended Abstract (BWW), pp. 13–17.
ICFP-2015-Sheeran #design #functional #programming #years after: Functional programming and hardware design: still interesting after all these years (MS), p. 165.
PLDI-2015-RenJKAK #execution #performance #recursion #source code: Efficient execution of recursive programs on commodity vector hardware (BR, YJ, SK, KA, MK), pp. 509–520.
ASPLOS-2015-MatveevS #hybrid #memory management #scalability #transaction: Reduced Hardware NOrec: A Safe and Scalable Hybrid Transactional Memory (AM, NS), pp. 59–71.
ASPLOS-2015-ZhangWSM #data flow #design #information management #security: A Hardware Design Language for Timing-Sensitive Information-Flow Security (DZ, YW, GES, ACM), pp. 503–516.
CASE-2015-ChuFRSKT #approach #automation #integration: A LC-MS integration approach in life science automation: Hardware integration and software integration (XC, HF, TR, NS, MK, KT), pp. 979–984.
CASE-2015-PellicciariABBB #industrial #named: AREUS — Innovative hardware and software for sustainable industrial robotics (MP, AA, KB, GB, NB, BL, DM), pp. 1325–1332.
DAC-2015-RahimiCMGB #clustering #embedded #memory management #scheduling #variability: Task scheduling strategies to mitigate hardware variability in embedded shared memory clusters (AR, DC, AM, RKG, LB), p. 6.
DAC-2015-WachsI #challenge #design #integration #security: Design and integration challenges of building security hardware IP (MW, DI), p. 6.
DAC-2015-ZhouAZYUGUJ #detection #embedded #using: Detecting hardware trojans using backside optical imaging of embedded watermarks (BZ, RA, MZ, TY, AU, BBG, MSÜ, AJ), p. 6.
DATE-2015-CakirM #clustering #correlation #detection #using: Hardware Trojan detection for gate-level ICs using signal correlation based clustering (BÇ, SM), pp. 471–476.
DATE-2015-CourbonLFT #detection #performance: A high efficiency hardware trojan detection technique based on fast SEM imaging (FC, PLM, JJAF, AT), pp. 788–793.
DATE-2015-DengFDWLTINLCW #fault #network: Retraining-based timing error mitigation for hardware neural networks (JD, YF, ZD, YW, HL, OT, PI, DN, XL, YC, CW), pp. 593–596.
DATE-2015-DinizSDBH #architecture #performance #standard #video: A deblocking filter hardware architecture for the high efficiency video coding standard (CMD, MS, FVD, SB, JH), pp. 1509–1514.
DATE-2015-DupuisBFNR #testing: New testing procedure for finding insertion sites of stealthy hardware trojans (SD, PSB, MLF, GDN, BR), pp. 776–781.
DATE-2015-FrancqF #detection: Introduction to hardware trojan detection methods (JF, FF), pp. 770–775.
DATE-2015-JiRML #implementation #logic #network #probability #using: A hardware implementation of a radial basis function neural network using stochastic logic (YJ, FR, CM, DJL), pp. 880–883.
DATE-2015-KalaliH #2d #adaptation #energy: A low energy 2D adaptive median filter hardware (EK, IH), pp. 725–729.
DATE-2015-LeeJG #functional #performance #simulation: Dynamic power and performance back-annotation for fast and accurate functional hardware simulation (DL, LKJ, AG), pp. 1126–1131.
DATE-2015-LiuDNL #named #realtime: FastTree: a hardware KD-tree construction acceleration engine for real-time ray tracing (XL, YD, YN, ZL), pp. 1595–1598.
DATE-2015-NgoEBDGNRR #detection #metric: Hardware trojan detection by delay and electromagnetic measurements (XTN, IE, SB, JLD, SG, ZN, JBR, BR), pp. 782–787.
DATE-2015-PaulinoFBC #configuration management #execution #using: Transparent acceleration of program execution using reconfigurable hardware (NMCP, JCF, JB, JMPC), pp. 1066–1071.
DATE-2015-ReehmanCCS #approach #architecture #memory management #parallel: In-place memory mapping approach for optimized parallel hardware interleaver architectures (SUR, CC, PC, AS), pp. 896–899.
DATE-2015-SkalickySLF #framework #runtime: A unified hardware/software MPSoC system construction and run-time framework (SS, AGS, SL, MF), pp. 301–304.
DATE-2015-SonghoriMLK #automation #data analysis #framework #named: AHEAD: automated framework for hardware accelerated iterative data analysis (EMS, AM, XL, FK), pp. 942–947.
DATE-2015-ThomasFCG: Transparent linking of compiled software and synthesized hardware (DBT, STF, GAC, DRG), pp. 1084–1089.
DATE-2015-TuYOLW #architecture #configuration management #named: RNA: a reconfigurable architecture for hardware neural acceleration (FT, SY, PO, LL, SW), pp. 695–700.
DATE-2015-WartelKGBSTQLMB #analysis #case study #platform: Timing analysis of an avionics case study on complex hardware/software platforms (FW, LK, AG, AB, ZRS, BT, EQ, CL, EM, IB, JA, LCG, TV, FJC), pp. 397–402.
DATE-2015-YazdanbakhshMTP #approximate #design #named: Axilog: language support for approximate hardware design (AY, DM, BT, JP, AN, SS, KR, NR, RJ, AR, HE, KB), pp. 812–817.
DATE-2015-ZhangJSPHP #manycore #named #pipes and filters: E-pipeline: elastic hardware/software pipelines on a many-core fabric (XZ, HJ, MS, JP, JH, SP), pp. 363–368.
HPCA-2015-JinPSCSZ #fault #named: FTXen: Making hypervisor resilient to hardware faults on relaxed cores (XJ, SP, TS, RC, ZS, YZ), pp. 451–462.
HPDC-2015-BestaH #memory management #transaction: Accelerating Irregular Computations with Hardware Transactional Memory and Active Messages (MB, TH), pp. 161–172.
LCTES-2015-ProcterHGBA #design #implementation #semantics #verification: Semantics Driven Hardware Design, Implementation, and Verification with ReWire (AMP, WLH, IG, MB, GA), p. 10.
PPoPP-2015-HaidarDLTD #linear #platform #towards: Towards batched linear solvers on accelerated hardware platforms (AH, TD, PL, ST, JJD), pp. 261–262.
PPoPP-2015-XiangS #clustering #transaction: Software partitioning of hardware transactions (LX, MLS), pp. 76–86.
CAV-2015-VijayaraghavanC #composition #deduction #design #multi #verification: Modular Deductive Verification of Multiprocessor Hardware Designs (MV, AC, A, ND), pp. 109–127.
QoSA-2014-EtxeberriaTCS #nondeterminism #parametricity: Performance-based selection of software and hardware features under parameter uncertainty (LE, CT, VC, GS), pp. 23–32.
SIGMOD-2014-Herlihy #memory management #transaction: Fun with hardware transactional memory (MH), p. 575.
SIGMOD-2014-LevandoskiLSBD: Indexing on modern hardware: hekaton and beyond (JJL, DBL, SS, AB, CD), pp. 717–720.
VLDB-2014-BressHSKMS #named: Ocelot/HyPE: Optimized Data Processing on Heterogeneous Hardware (SB, MH, MS, BK, VM, GS), pp. 1609–1612.
VLDB-2014-He #approximate #challenge #data transformation: When Data Management Systems Meet Approximate Hardware: Challenges and Opportunities (BH), pp. 877–880.
MSR-2014-HindleWRBCR #energy #framework #mining #named #repository: GreenMiner: a hardware based mining software repositories software energy consumption framework (AH, AW, KR, EJB, JCC, SR), pp. 12–21.
FM-2014-MaricS #memory management #transaction #verification: Verification of a Transactional Memory Manager under Hardware Failures and Restarts (OM, CS), pp. 449–464.
IFM-2014-JakobsPWW #verification: Integrating Software and Hardware Verification (MCJ, MP, HW, TW), pp. 307–322.
CHI-2014-LindtnerHD #human-computer: Emerging sites of HCI innovation: hackerspaces, hardware startups & incubators (SL, GDH, PD), pp. 439–448.
HCI-AIMT-2014-Man #using #video: Analysing Emotional Video Using Consumer EEG Hardware (JdM), pp. 729–738.
ASPLOS-2014-AgrawalPPTTL #named #parallel: Rhythm: harnessing data parallel hardware for server workloads (SRA, VP, JP, JT, DT, ARL), pp. 19–34.
ASPLOS-2014-ArulrajJL #memory management: Leveraging the short-term memory of hardware to diagnose production-run software failures (JA, GJ, SL), pp. 207–222.
ASPLOS-2014-LuponGMSMSD #float #multi: Speculative hardware/software co-designed floating-point multiply-add fusion (ML, EG, GM, SS, RM, KS, DRD), pp. 623–638.
ASPLOS-2014-RuwaseKGM #approach #named: Guardrail: a high fidelity approach to protecting hardware devices from buggy drivers (OR, MAK, PBG, TCM), pp. 655–670.
CGO-2014-JimboreanKSBK #approach #compilation #scalability: Fix the code. Don’t tweak the hardware: A new compiler approach to Voltage-Frequency scaling (AJ, KK, VS, DBS, SK), p. 262.
DAC-2014-CocchiBCW #integration: Circuit Camouflage Integration for Hardware IP Protection (RPC, JPB, LWC, BJW), p. 5.
DAC-2014-CuiMSW #detection #runtime #synthesis: High-Level Synthesis for Run-Time Hardware Trojan Detection and Recovery (XC, KM, LS, KW), p. 6.
DAC-2014-HollerDKSF #co-evolution #design #encryption: Hardware/Software Co-Design of Elliptic-Curve Cryptography for Resource-Constrained Applications (AH, ND, CK, CS, TF), p. 6.
DAC-2014-HuWTT #monitoring #network #security: System-Level Security for Network Processors with Hardware Monitors (KH, TW, TT, RT), p. 6.
DAC-2014-KosmidisQAFWC #certification: Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware (LK, EQ, JA, GF, FW, FJC), p. 6.
DAC-2014-LiuHM #detection #statistics: Hardware Trojan Detection through Golden Chip-Free Statistical Side-Channel Fingerprinting (YL, KH, YM), p. 6.
DAC-2014-SullivanBZZJ #functional #identification #named: FIGHT-Metric: Functional Identification of Gate-Level Hardware Trustworthiness (DS, JB, GZ, SZ, YJ), p. 4.
DAC-2014-TsoutsosKM #design: Advanced Techniques for Designing Stealthy Hardware Trojans (NGT, CK, MM), p. 4.
DAC-2014-ZhangPL #power management: Low Power GPGPU Computation with Imprecise Hardware (HZ, MP, JL), p. 6.
DATE-2014-BraojosDBAA #approach #manycore #power management: Hardware/software approach for code synchronization in low-power multi-core sensor nodes (RB, AYD, IB, GA, DA), pp. 1–6.
DATE-2014-BurgioDMCB #clustering #programmable #scalability: A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters (PB, RD, AM, PC, LB), pp. 1–4.
DATE-2014-BurgioTCMB #clustering #embedded #memory management #parallel: Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters (PB, GT, FC, AM, LB), pp. 1–6.
DATE-2014-DimitrakopoulosSPTMC #parallel #synthesis #thread: Hardware primitives for the synthesis of multithreaded elastic systems (GD, IS, AP, KT, PMM, JC), pp. 1–4.
DATE-2014-HamdiouiDNSBT: Hacking and protecting IC hardware (SH, JLD, GDN, FS, GvB, MT), pp. 1–7.
DATE-2014-LiuBC #image: Image progressive acquisition for hardware systems (JL, CSB, PYKC), pp. 1–6.
DATE-2014-PaulKBP #energy #memory management: Energy-efficient hardware acceleration through computing in the memory (SP, RK, SB, RP), pp. 1–6.
DATE-2014-SanderSDBBBMKALHRHH #manycore: Hardware virtualization support for shared resources in mixed-criticality multicore systems (OS, TS, VVD, SB, FB, JB, HUM, DK, DA, EL, JH, AR, CH, AH), pp. 1–6.
DATE-2014-SchollW #implementation #set: Hardware implementation of a Reed-Solomon soft decoder based on information set decoding (SS, NW), pp. 1–6.
DATE-2014-TtofisT #image #realtime: High-quality real-time hardware stereo matching based on guided image filtering (CT, TT), pp. 1–6.
HPCA-2014-LiuXGZC #concurrent #consistency #memory management #transaction #virtual machine: Concurrent and consistent virtual machine introspection with hardware transactional memory (YL, YX, HG, BZ, HC), pp. 416–427.
ISMM-2014-BaconCS #configuration management #garbage collection #parallel #realtime: Parallel real-time garbage collection of multiple heaps in reconfigurable hardware (DFB, PC, SS), pp. 117–127.
ISMM-2014-RitsonUJ #garbage collection #memory management #transaction: Exploring garbage collection with haswell hardware transactional memory (CGR, TU, REJ), pp. 105–115.
PDP-2014-BuonoMMV #architecture #manycore #message passing #optimisation #thread #using: Optimizing Message-Passing on Multicore Architectures Using Hardware Multi-threading (DB, TDM, GM, MV), pp. 262–270.
PDP-2014-ItoF #analysis #problem #resource management #using: An Experimental Analysis for Hardware Resource Management Using a New Strip Packing Problem (RI, NF), pp. 360–364.
PDP-2014-ManciniMMMT #distributed #manycore #simulation #verification: System Level Formal Verification via Distributed Multi-core Hardware in the Loop Simulation (TM, FM, AM, IM, ET), pp. 734–742.
PPoPP-2014-OdairaCT #interpreter #memory management #ruby #transaction: Eliminating global interpreter locks in ruby through hardware transactional memory (RO, JGC, HT), pp. 131–142.
PPoPP-2014-PetrovicRS #concurrent #message passing #performance #thread: Leveraging hardware message passing for efficient thread synchronization (DP, TR, AS), pp. 143–154.
ICTSS-2014-ChabotP #embedded #framework #monitoring: A Customizable Monitoring Infrastructure for Hardware/Software Embedded Systems (MC, LP), pp. 173–179.
VLDB-2013-LevandoskiLS #named: LLAMA: A Cache/Storage Subsystem for Modern Hardware (JJL, DBL, SS), pp. 877–888.
VLDB-2013-Lomet #approach #database #sql: Microsoft SQL Server’s Integrated Database Approach for Modern Applications and Hardware (DBL), pp. 1178–1179.
SIGITE-2013-HillC #development #education #framework #low cost #open source #platform #programming #student #using: Using a low-cost open source hardware development platform in teaching young students programming skills (LWH, SC), pp. 63–68.
SCAM-2013-FlochYMMMNALSDCWS #design #framework #named #prototype: GeCoS: A framework for prototyping custom hardware design flows (AF, TY, AEM, AM, KM, MN, MA, LL, NS, SD, FC, CW, OS), pp. 100–105.
CEFP-2013-Kuper #specification: Hardware Specification with CλaSH (JK), pp. 336–380.
ECOOP-2013-AuerbachBCFR #compilation #configuration management #graph: The Shape of Things to Run — Compiling Complex Stream Graphs to Reconfigurable Hardware in Lime (JSA, DFB, PC, SF, RMR), pp. 679–706.
OOPSLA-2013-CarbinMR #reliability #source code #verification: Verifying quantitative reliability for programs that execute on unreliable hardware (MC, SM, MCR), pp. 33–52.
ESEC-FSE-2013-Nenashev #automation #named #programmable #re-engineering: PHRT: a model and programmable tool for hardware reengineering automation (ON), pp. 719–722.
ASPLOS-2013-ArulrajCJL #performance: Production-run software failure diagnosis via hardware performance counters (JA, PCC, GJ, SL), pp. 101–112.
ASPLOS-2013-GrossmanKBTDILSTYS #fine-grained: Hardware support for fine-grained event-driven computation in Anton 2 (JPG, JK, JAB, MT, ROD, DJI, RHL, UBS, BT, CY, DES), pp. 549–560.
ASPLOS-2013-KangW #approach: To hardware prefetch or not to prefetch?: a virtualized environment study and core binding approach (HK, JLW), pp. 357–368.
ASPLOS-2013-RaghavanESPPWM #testing: Computational sprinting on a hardware/software testbed (AR, LE, LS, MCP, KPP, TFW, MMKM), pp. 155–166.
ASPLOS-2013-SungKA #named #nondeterminism #performance: DeNovoND: efficient hardware support for disciplined non-determinism (HS, RK, SVA), pp. 13–26.
ASPLOS-2013-WangW #named #optimisation #performance: TSO_ATOMICITY: efficient hardware primitive for TSO-preserving region optimizations (CW, YW), pp. 509–520.
CASE-2013-VenatorLN #architecture #industrial #mobile: Hardware and software architecture of ABBY: An industrial mobile manipulator (EV, GSL, WSN), pp. 324–329.
DAC-2013-AvinashBEPP #energy #fault: Improving energy gains of inexact DSP hardware through reciprocative error compensation (LA, AB, CCE, KVP, CP), p. 8.
DAC-2013-ChandrikakuttyUTW #monitoring #network: High-performance hardware monitors to protect network processors from data plane attacks (HC, DU, RT, TW), p. 6.
DAC-2013-WangK #control flow #detection #kernel #named #performance #using: NumChecker: detecting kernel control-flow modifying rootkits by using hardware performance counters (XW, RK), p. 7.
DAC-2013-WeiP #detection: The undetectable and unprovable hardware trojan horse (SW, MP), p. 2.
DAC-2013-ZhangYWSX #named #trust #verification: VeriTrust: verification for hardware trust (JZ, FY, LW, ZS, QX), p. 8.
DATE-2013-HuNRK #detection #multimodal #using: High-sensitivity hardware trojan detection using multimodal characterization (KH, ANN, SR, FK), pp. 1271–1276.
DATE-2013-LeestT #security: Anti-counterfeiting with hardware intrinsic security (VvdL, PT), pp. 1137–1142.
DATE-2013-LotfianJ #architecture #power management #smarttech #using: An ultra-low power hardware accelerator architecture for wearable computers using dynamic time warping (RL, RJ), pp. 913–916.
DATE-2013-ObergMSK #framework #testing: A practical testing framework for isolating hardware timing channels (JO, SM, TS, RK), pp. 1281–1284.
DATE-2013-Pham-QuocHWABB #design #hybrid: Hybrid interconnect design for heterogeneous hardware accelerators (CPQ, JH, SW, ZAA, JB, KB), pp. 843–846.
DATE-2013-RehmanSAKCH #reliability: Leveraging variable function resilience for selective software reliability on unreliable hardware (SR, MS, PVA, FK, JJC, JH), pp. 1759–1764.
DATE-2013-SagstetterLSWBHJPPC #architecture #challenge #design #security: Security challenges in automotive hardware/software architecture design (FS, ML, SS, MW, AB, WRH, SJ, TP, AP, SC), pp. 458–463.
DATE-2013-ThabetLAPD #architecture #flexibility #manycore #performance: An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture (FT, YL, CA, JMP, RD), pp. 531–534.
DATE-2013-YalcinUC #detection #fault #memory management #named #transaction #using: FaulTM: error detection and recovery using hardware transactional memory (GY, OSÜ, AC), pp. 220–225.
PDP-2013-WuGTSGFS #framework #named: SecMon: A Secure Introspection Framework for Hardware Virtualization (XW, YG, XT, YS, BG, BF, YS), pp. 282–286.
PPoPP-2013-AfekLM #programming: Programming with hardware lock elision (YA, AL, AM), pp. 295–296.
PPoPP-2013-DiceLLLM #algorithm #memory management #transaction #using: Using hardware transactional memory to correct and simplify and readers-writer lock algorithm (DD, YL, YL, VL, MM), pp. 261–270.
CAV-2013-BraibantC #synthesis #verification: Formal Verification of Hardware Synthesis (TB, AC), pp. 213–228.
VLDB-2012-PorobicPBTA: OLTP on Hardware Islands (DP, IP, MB, PT, AA), pp. 1447–1458.
ITiCSE-2012-Black #cpu #design #education: A hardware simulator for teaching CPU design (MB), p. 380.
ITiCSE-2012-GoldweberDJ #operating system #using: Supporting operating systems projects using the μMPS2 hardware simulator (MG, RD, TJ), pp. 63–68.
TFPIE-2012-ODonnell #education #functional #using: Connecting the Dots: Computer Systems Education using a Functional Hardware Description Language (JTO), pp. 20–39.
CSCW-2012-MellisB #arduino #collaboration #open source: Collaboration in open-source hardware: third-party variations on the arduino duemilanove (DM, LB), pp. 1175–1178.
KDD-2012-RoyTA #manycore #performance: Efficient frequent item counting in multi-core hardware (PR, JT, GA), pp. 1451–1459.
OOPSLA-2012-SartorE #concurrent #java #manycore #performance #thread: Exploring multi-threaded Java application performance on multicore hardware (JBS, LE), pp. 281–296.
AdaEurope-2012-GregertsenS #execution #performance #using: Improving the Performance of Execution Time Control by Using a Hardware Time Management Unit (KNG, AS), pp. 177–192.
PLDI-2012-BaconCS #configuration management #garbage collection #realtime: And then there were none: a stall-free real-time garbage collector for reconfigurable hardware (DFB, PC, SS), pp. 23–34.
PPDP-2012-TriossiORF #compilation #parallel: Compiling CHR to parallel hardware (AT, SO, AR, TWF), pp. 173–184.
ASPLOS-2012-FerdmanAKVAJKPAF #case study: Clearing the clouds: a study of emerging scale-out workloads on modern hardware (MF, AA, YOK, SV, MA, DJ, CK, ADP, AA, BF), pp. 37–48.
ASPLOS-2012-KingDA #automation #generative #interface: Automatic generation of hardware/software interfaces (MK, ND, A), pp. 325–336.
DAC-2012-BachrachVRLWAWA #embedded #named #scala: Chisel: constructing hardware in a Scala embedded language (JB, HV, BR, YL, AW, RA, JW, KA), pp. 1216–1225.
DAC-2012-ChanSSM #specification #synthesis: Specification and synthesis of hardware checkpointing and rollback mechanisms (CC, DSN, DS, SM), pp. 1226–1232.
DAC-2012-HuangLR #energy #trade-off #using: A methodology for energy-quality tradeoff using imprecise hardware (JH, JL, GR), pp. 504–509.
DAC-2012-HuLWR #array #using: Hardware realization of BSB recall function using memristor crossbar arrays (MH, HL, QW, GSR), pp. 498–503.
DAC-2012-MalburgFF #automation #design #locality #metric #using: Automated feature localization for hardware designs using coverage metrics (JM, AF, GF), pp. 941–946.
DAC-2012-MiddendorfBH #recursion #synthesis: Hardware synthesis of recursive functions through partial stream rewriting (LM, CB, CH), pp. 1207–1215.
DAC-2012-WeiLKP #benchmark #metric: Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry (SW, KL, FK, MP), pp. 90–95.
DATE-2012-Al-HashimiM #framework #platform #question #verification: Accelerators and emulators: Can they become the platform of choice for hardware verification? (BMAH, RM), p. 430.
DATE-2012-BeaumontHN #architecture #execution #replication #security #using: SAFER PATH: Security architecture using fragmented execution and replication for protection against trojaned hardware (MRB, BDH, TN), pp. 1000–1005.
DATE-2012-LiDT #authentication #detection #framework #self: A sensor-assisted self-authentication framework for hardware trojan detection (ML, AD, MT), pp. 1331–1336.
DATE-2012-LiRP #embedded #named: Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors (TL, RGR, SP), pp. 875–880.
DATE-2012-StipicTZCUV #data access #metadata #named #performance: TagTM — accelerating STMs with hardware tags for fast meta-data access (SS, ST, FZ, AC, OSÜ, MV), pp. 39–44.
DATE-2012-TtofisT #adaptation #algorithm #implementation #realtime #towards: Towards accurate hardware stereo correspondence: A real-time FPGA implementation of a segmentation-based adaptive support weight algorithm (CT, TT), pp. 703–708.
HPCA-2012-BensonCFHGNS #design #implementation #integration: Design, integration and implementation of the DySER hardware accelerator into OpenSPARC (JB, RC, CF, CHH, VG, TN, KS), pp. 115–126.
HPCA-2012-NegiGAGS #lazy evaluation #memory management #named #scalability #transaction: π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory (AN, JRTG, MEA, JMG, PS), pp. 141–152.
HPCA-2012-QiONMT #named #symmetry: Pacman: Tolerating asymmetric data races with unintrusive hardware (SQ, NO, LON, AM, JT), pp. 349–360.
ISMM-2012-InoueN #identification #java #source code: Identifying the sources of cache misses in Java programs without relying on hardware counters (HI, TN), pp. 133–142.
OSDI-2012-KotlaRRSW #data access #named #using: Pasture: Secure Offline Data Access Using Commodity Trusted Hardware (RK, TR, IR, PS, BW), pp. 321–334.
PDP-2012-Gaona-RamirezGAF #energy #memory management #transaction: Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems (EGR, JRTG, MEA, JF), pp. 221–228.
PDP-2012-Kunkel0 #architecture #file system #functional #modelling #named #parallel #representation: IOPm — Modeling the I/O Path with a Functional Representation of Parallel File System and Hardware Architecture (JMK, TL), pp. 554–561.
ISSTA-2012-Walcott-JusticeMS #monitoring #named #testing: THeME: a system for testing by hardware monitoring events (KWJ, JM, MLS), pp. 12–22.
SIGMOD-2011-BajajS #database #named #privacy: TrustedDB: a trusted hardware based database with privacy and data confidentiality (SB, RS), pp. 205–216.
VLDB-2011-BajajS #database #named #outsourcing: TrustedDB: A Trusted Hardware based Outsourced Database Engine (SB, RS), pp. 1359–1362.
VLDB-2011-Neumann #compilation #performance #query: Efficiently Compiling Efficient Query Plans for Modern Hardware (TN0), pp. 539–550.
ICFP-2011-GhicaSS #compilation #geometry #recursion #synthesis: Geometry of synthesis iv: compiling affine recursion into static hardware (DRG, AIS, SS), pp. 221–233.
IFL-2011-Megacz #design: Hardware Design with Generalized Arrows (AM), pp. 164–180.
AdaEurope-2011-Burns #parallel #programming language #realtime: Programming Languages for Real-Time Applications Executing on Parallel Hardware (AB), pp. 193–195.
PLDI-2011-LiTOKCSH #data flow #named: Caisson: a hardware description language for secure information flow (XL, MT, JO, VK, FTC, TS, BH), pp. 109–120.
ASE-2011-LiXBLM #formal method #interface #specification: Formalizing hardware/software interface specifications (JL, FX, TB, VL, CM), pp. 143–152.
ICSE-2011-SoffaWM #debugging #testing: Exploiting hardware advances for software testing and debugging (MLS, KRW, JM), pp. 888–891.
SAC-2011-LinXYYZGQCG #anti #named #using: SPAD: software protection through anti-debugging using hardware virtualization (QL, MX, MY, PY, MZ, SG, ZQ, KC, HG), pp. 623–624.
ASPLOS-2011-CasperOHBKO #memory management #transaction: Hardware acceleration of transactional memory on commodity systems (JC, TO, SH, NGB, CK, KO), pp. 27–38.
ASPLOS-2011-DalessandroCWLMSS #case study #effectiveness #hybrid #memory management #transaction: Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory (LD, FC, SW, YL, MM, MLS, MFS), pp. 39–52.
ASPLOS-2011-EsmaeilzadehCXBM #performance #roadmap #scalability: Looking back on the language and hardware revolutions: measured power, performance, and scaling (HE, TC, XY, SMB, KSM), pp. 319–332.
ASPLOS-2011-RyzhykKMRVH #reliability #reuse #verification: Improved device driver reliability through hardware verification reuse (LR, JK, BM, AR, MV, GH), pp. 133–144.
DAC-2011-AuerbachBCRS #object-oriented: Virtualization of heterogeneous machines hardware description in a synthesizable object-oriented language (JSA, DFB, PC, RMR, SS), pp. 890–894.
DAC-2011-NguyenWSK #abstraction: Formal hardware/software co-verification by interval property checking with abstraction (MDN, MW, DS, WK), pp. 510–515.
DATE-2011-AgyekumN #communication #robust: A delay-insensitive bus-invert code and hardware support for robust asynchronous global communication (MYA, SMN), pp. 1370–1375.
DATE-2011-AliCMB #encryption #multi #security: Multi-level attacks: An emerging security concern for cryptographic hardware (SA, RSC, DM, SB), pp. 1176–1179.
DATE-2011-ChangMFWHYN #architecture #hybrid #optimisation: Optimization of stateful hardware acceleration in hybrid architectures (XC, YM, HF, KW, RH, HY, TN), pp. 567–570.
DATE-2011-Cilardo #configuration management: The potential of reconfigurable hardware for HPC cryptanalysis of SHA-1 (AC), pp. 998–1003.
DATE-2011-KunzGW #memory management #performance #transaction: Improving the efficiency of a hardware transactional memory on an NoC-based MPSoC (LK, GG, FRW), pp. 1168–1171.
DATE-2011-KyrkouTT #detection: Depth-directed hardware object detection (CK, CT, TT), pp. 1442–1447.
DATE-2011-TendulkarPNKNK #communication #runtime: Fine-grain OpenMP runtime support with explicit communication hardware primitives (PT, VP, GN, SGK, DSN, MK), pp. 891–894.
DATE-2011-WagnerL #distributed #framework: Distributed hardware matcher framework for SoC survivability (IW, SLL), pp. 305–310.
DATE-2011-ZattSBH #architecture #estimation #parallel #pipes and filters #throughput #video: Multi-level pipelined parallel hardware architecture for high throughput motion and disparity estimation in Multiview Video Coding (BZ, MS, SB, JH), pp. 1448–1453.
DATE-2011-ZhangT #detection #named #network: RON: An on-chip ring oscillator network for hardware Trojan detection (XZ, MT), pp. 1638–1643.
HPCA-2011-CarreteroVARMG #process #using: Hardware/software-based diagnosis of load-store queues using expandable activity logs (JC, XV, JA, TR, MM, AG), pp. 321–331.
HPCA-2011-LiuLNMMH: Hardware/software techniques for DRAM thermal management (SL, BL, AN, SOM, GM, NH), pp. 515–525.
TACAS-2011-AlglaveMSS #named #testing: Litmus: Running Tests against Hardware (JA, LM, SS, PS), pp. 41–44.
CAV-2011-MullerP #interface #verification: Complete Formal Hardware Verification of Interfaces for a FlexRay-Like Bus (CAM, WJP), pp. 633–648.
VLDB-2010-SadoghiJLSS #algorithm #configuration management #performance: Efficient Event Processing through Reconfigurable Hardware for Algorithmic Trading (MS, HAJ, ML, WS, HS), pp. 1525–1528.
KEOD-2010-BarrosoAG #encryption #in the cloud #process: Key Management Process on the Hardware Cryptographic Module in the Cloud Computing (JMDB, LJA, PGG), pp. 493–496.
SEKE-2010-BinGHMMPRST #ontology #tool support #verification: Ontology-Based Tools in the Service of Hardware Verification (EB, AG, KH, EM, RM, OP, MR, GS, ET), pp. 303–308.
OOPSLA-2010-KouP #object-oriented #question: From OO to FPGA: fitting round objects into square hardware? (SK, JP), pp. 109–124.
AdaEurope-2010-White #ada #scheduling #using: Using Hardware Support for Scheduling with Ada (RW), pp. 125–138.
FSE-2010-YilmazP: Combining hardware and software instrumentation to classify program executions (CY, AAP), pp. 67–76.
SAC-2010-SiderisMP #java: A hardware peripheral for Java bytecodes translation acceleration (IS, NKM, KZP), pp. 552–553.
ASPLOS-2010-NeelakantamDZ #evaluation: A real system evaluation of hardware atomicity for software speculation (NN, DRD, CBZ), pp. 29–38.
CASE-2010-LamS: Accelerating shortest path computations in hardware (SKL, TS), pp. 63–68.
CGO-2010-ChenVHLRYCZ #compilation: Taming hardware event samples for FDO compilation (DC, NV, RH, SwL, VR, PY, WC, WZ), pp. 42–52.
DAC-2010-Breuer #bound: Hardware that produces bounded rather than exact results (MAB), pp. 871–876.
DAC-2010-ChakradharR #parallel: Best-effort computing: re-thinking parallel software and hardware (STC, AR), pp. 865–870.
DAC-2010-ChippaMRRC #algorithm #design #energy #performance #scalability: Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency (VKC, DM, AR, KR, STC), pp. 555–560.
DAC-2010-KinsmanN #algorithm #design #robust: Robust design methods for hardware accelerators for iterative algorithms in scientific computing (ABK, NN), pp. 254–257.
DAC-2010-WeiMP #security: Gate-level characterization: foundations and hardware security applications (SW, SM, MP), pp. 222–227.
DATE-2010-AgyekumN #communication #robust: An error-correcting unordered code and hardware support for robust asynchronous global communication (MYA, SMN), pp. 765–770.
DATE-2010-AhlendorfG #challenge #design #monitoring #power management: Hardware / software design challenges of low-power sensor nodes for condition monitoring (HA, LG), p. 659.
DATE-2010-AkinSH #configuration management #estimation #multi: A reconfigurable hardware for one bit transform based multiple reference frame Motion Estimation (AA, GS, IH), pp. 393–398.
DATE-2010-DasMZC #detection #information management #memory management: Detecting/preventing information leakage on the memory bus due to malicious hardware (AD, GM, JZ, ANC), pp. 861–866.
DATE-2010-GiraldoMJM #using: A HMMER hardware accelerator using divergences (JFEG, NM, RPJ, ACMAdM), pp. 405–410.
DATE-2010-GuFP #compilation #scheduling: Path-based scheduling in a hardware compiler (RG, AF, RNP), pp. 1317–1320.
DATE-2010-HadjitheophanousTGT #3d #re-engineering #realtime #towards: Towards hardware stereoscopic 3D reconstruction a real-time FPGA computation of the disparity map (SH, CT, ASG, TT), pp. 1743–1748.
DATE-2010-LopezSPLC #image: Exploration of hardware sharing for image encoders (SL, RS, PGP, WL, PYKC), pp. 1737–1742.
DATE-2010-Schlager #interactive #performance: Increasing the power efficiency of PCs by improving the hardware/OS interaction (CS), p. 1005.
HPCA-2010-Arvind #question: Is hardware innovation over? (A), p. 1.
HPCA-2010-DoudalisP #execution #named: HARE: Hardware assisted reverse execution (ID, MP), pp. 1–12.
PDP-2010-BroquedisCMFGMTN #framework #named: hwloc: A Generic Framework for Managing Hardware Affinities in HPC Applications (FB, JCO, SM, NF, BG, GM, ST, RN), pp. 180–186.
PDP-2010-FloresAA #energy #using: Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects (AF, JLA, MEA), pp. 147–154.
PPoPP-2010-Arvind #question: Is hardware innovation over? (A), pp. 103–104.
FASE-2010-LiXBLM #approach: An Automata-Theoretic Approach to Hardware/Software Co-verification (JL, FX, TB, VL, CM), pp. 248–262.
CAV-2010-LiXBL #analysis #automaton #performance #reachability: Efficient Reachability Analysis of Büchi Pushdown Systems for Hardware/Software Co-verification (JL, FX, TB, VL), pp. 339–353.
ICST-2010-SyedRW #fault #question: Does Hardware Configuration and Processor Load Impact Software Fault Observability? (RAS, BR, LAW), pp. 285–294.
SIGITE-2009-Stanley #architecture #education #logic #network #operating system #simulation #using: Using digital logic simulation as a teaching aid in discrete mathematics, hardware and operating systems, networking, computer organization and computer architecture: a workshop outline (TDS), pp. 1–2.
IFM-2009-Cook #bound #synthesis: Taming the Unbounded for Hardware Synthesis (BC), p. 39.
Haskell-2009-BaaijKKGM #haskell #tool support: Tool DemonstrationCLasHFrom Haskell to Hardware (CB, MK, JK, MG, BM).
HCI-NIMT-2009-VarcholikLN #interactive #multi #named #research #testing: TACTUS: A Hardware and Software Testbed for Research in Multi-Touch Interaction (PV, JJLJ, DMN), pp. 523–532.
ECOOP-2009-Click #co-evolution #design #java: Java on 1000 Cores: Tales of Hardware/Software Co-design (CC), p. 444.
OOPSLA-2009-HaABM #concurrent #dynamic analysis #framework #manycore: A concurrent dynamic analysis framework for multicore hardware (JH, MA, SMB, KSM), pp. 155–174.
OOPSLA-2009-InoueN #how #java #monitoring #performance #virtual machine: How a Java VM can get more from a hardware performance monitor (HI, TN), pp. 137–154.
PLDI-2009-MehraraHHM #low cost #memory management #transaction #using: Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory (MM, JH, PCH, SAM), pp. 166–176.
SAC-2009-QiuLS #embedded #framework #optimisation #platform #realtime: Heterogeneous real-time embedded software optimization considering hardware platform (MQ, HL, EHMS), pp. 1637–1641.
GPCE-2009-Nikhil #design #using: Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design) (RSN), pp. 1–2.
ASPLOS-2009-DiceLMN #experience #implementation #memory management #transaction: Early experience with a commercial hardware transactional memory implementation (DD, YL, MM, DN), pp. 157–168.
CC-2009-KnightsMSMD #optimisation: Blind Optimization for Exploiting Hardware Features (DK, TM, PFS, MCM, AD), pp. 251–265.
CGO-2009-CuthbertsonVBAS #approach #monitoring #optimisation #performance #virtual machine: A Practical Approach to Hardware Performance Monitoring Based Dynamic Optimizations in a Production JVM (JC, SV, KB, AA, EK, US), pp. 190–199.
DAC-2009-BorgstromHWADCMCN #hybrid #prototype #question: System prototypes: virtual, hardware or hybrid? (TB, EH, RW, DA, AD, RC, OM, CC, AN), pp. 1–3.
DAC-2009-DengCS #authentication #performance #simulation: Hardware authentication leveraging performance limits in detailed simulations and emulations (DYD, AHC, GES), pp. 682–687.
DAC-2009-PotkonjakNNM #detection #using: Hardware Trojan horse detection using gate-level characterization (MP, AN, MN, TM), pp. 688–693.
DAC-2009-RaabeB #sketching: Synthesizing hardware from sketches (AR, RB), pp. 623–624.
DAC-2009-ReddiGSWBC #challenge #reliability #stack: Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack (VJR, SC, MSG, MDS, GYW, DMB), pp. 788–793.
DATE-2009-DabiriP: Hardware aging-based software metering (FD, MP), pp. 460–465.
DATE-2009-Gomez-PradoRCGB #data flow #graph #implementation #optimisation: Optimizing data flow graphs to minimize hardware implementation (DGP, QR, MJC, JG, EB), pp. 117–122.
DATE-2009-HaastregtK #automation #c #network #process #streaming #synthesis: Automated synthesis of streaming C applications to process networks in hardware (SvH, BK), pp. 890–893.
DATE-2009-HaoX #component #design #interface: Componentizing hardware/software interface design (KH, FX), pp. 232–237.
DATE-2009-HenzenCFF #evaluation: Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT (LH, FC, NF, WF), pp. 646–651.
DATE-2009-KhanK09a #architecture #co-evolution #design #multi: Hardware/software co-design architecture for thermal management of chip multiprocessors (OK, SK), pp. 952–957.
DATE-2009-LettninNBRGKRSR #verification: Semiformal verification of temporal properties in automotive hardware dependent software (DL, PKN, JB, JR, JG, TK, WR, VS, SR), pp. 1214–1217.
DATE-2009-OetjensGGN #automation #process: An automated flow for integrating hardware IP into the automotive systems engineering process (JHO, RG, JG, WN), pp. 1196–1201.
DATE-2009-ShafiqueBH #approach #design #parallel #performance #predict #video: A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec (MS, LB, JH), pp. 1434–1439.
DATE-2009-TasdizenKAH #architecture #configuration management #estimation #performance: A high performance reconfigurable Motion Estimation hardware architecture (OT, HK, AA, IH), pp. 882–885.
DATE-2009-WagnerB #manycore #named: Caspar: Hardware patching for multicore processors (IW, VB), pp. 658–663.
HPCA-2009-LiRKHA #architecture #fault #modelling: Accurate microarchitecture-level fault modeling for studying hardware faults (MLL, PR, URK, SKSH, SVA), pp. 105–116.
LCTES-2009-FidgeC #analysis #data flow: Integrating hardware and software information flow analyses (CJF, DC), pp. 157–166.
PPoPP-2009-AbadiHM #memory management #off the shelf #transaction #using: Transactional memory with strong atomicity using off-the-shelf memory protection hardware (MA, TH, MM), pp. 185–196.
PPoPP-2009-Quintana-OrtiIQG #linear #multi #platform: Solving dense linear systems on platforms with multiple hardware accelerators (GQO, FDI, ESQO, RAvdG), pp. 121–130.
SOSP-2009-KadavRS: Tolerating hardware device failures in software (AK, MJR, MMS), pp. 59–72.
ISSTA-2009-BotaschanjanH #fault #modelling #orthogonal #specification: Specifying the worst case: orthogonal modeling of hardware errors (JB, BH), pp. 273–284.
LICS-2009-Ghica #game studies #program analysis #semantics #synthesis: Applications of Game Semantics: From Program Analysis to Hardware Synthesis (DRG), pp. 17–26.
ECOOP-2008-HuangHBR #bound #object-oriented #programming: Liquid Metal: Object-Oriented Programming Across the Hardware/Software Boundary (SSH, AH, DFB, RMR), pp. 76–103.
PEPM-2008-FeiginM: Jones optimality and hardware virtualization: a report on work in progress (BF, AM), pp. 169–175.
PEPM-2008-GillenwaterMSZTGO #static typing #using: Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability (JG, GM, CS, AYZ, WT, JG, JO), pp. 41–50.
PLDI-2008-FengSDG #low level #source code #thread: Certifying low-level programs with hardware interrupts and preemptive threads (XF, ZS, YD, YG), pp. 170–182.
SAC-2008-LoTP #detection #implementation #network #regular expression: Hardware implementation for network intrusion detection rules with regular expression support (CTDL, YGT, KP), pp. 1535–1539.
SAC-2008-PerngCK #configuration management #embedded #platform: The minimization of hardware size in reconfigurable embedded platforms (NCP, JJC, TWK), pp. 1517–1522.
ASPLOS-2008-NightingalePCF #security: Parallelizing security checks on commodity hardware (EBN, DP, PMC, JF), pp. 308–318.
ASPLOS-2008-ShenZDLSZ #on the fly: Hardware counter driven on-the-fly request signatures (KS, MZ, SD, CL, CS, XZ), pp. 189–200.
ASPLOS-2008-TuckACT #analysis #named #optimisation: SoftSig: software-exposed hardware signatures for code analysis and optimization (JT, WA, LC, JT), pp. 145–156.
CC-2008-BergeronFD #compilation #configuration management #jit #off the shelf: Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs (EB, MF, JPD), pp. 178–192.
CGO-2008-FanPKM #reuse #scheduling #usability: Modulo scheduling for highly customized datapaths to increase hardware reusability (KF, HP, MK, SAM), pp. 124–133.
DAC-2008-AhmadiZ #analysis #approach #optimisation: Symbolic noise analysis approach to computational hardware optimization (AA, MZ), pp. 391–396.
DAC-2008-DavisTYZ #configuration management #satisfiability: A practical reconfigurable hardware accelerator for Boolean satisfiability solvers (JDD, ZT, FY, LZ), pp. 780–785.
DAC-2008-PatelP #design #named #reliability #security: SHIELD: a software hardware design methodology for security and reliability of MPSoCs (KP, SP), pp. 858–861.
DAC-2008-RoyKM: Protecting bus-based hardware IP by secret sharing (JAR, FK, ILM), pp. 846–851.
DATE-2008-AltCS #algorithm #architecture #detection #realtime: Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments (NA, CC, WS), pp. 176–181.
DATE-2008-ArteagaF #architecture #implementation #named #novel: GMDS: Hardware implementation of novel real output queuing architecture (RA, FT, REC, VdA, RS), pp. 1450–1455.
DATE-2008-RealCCDV #analysis: Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis (DR, CC, JC, MD, FV), pp. 1274–1279.
DATE-2008-RoginKFDR #automation #design #generative: Automatic Generation of Complex Properties for Hardware Designs (FR, TK, GF, RD, SR), pp. 545–548.
HPCA-2008-FenschC: An OS-based alternative to full hardware coherence on tiled CMPs (CF, MC), pp. 355–366.
ISMM-2008-GormanH: Supporting superpage allocation without additional hardware support (MG, PH), pp. 41–50.
OSDI-2008-ZeldovichKDK #memory management #policy #security #using: Hardware Enforcement of Application Security Policies Using Tagged Memory (NZ, HK, MD, CK), pp. 225–240.
PPoPP-2008-LevM #memory management #transaction #using: Split hardware transactions: true nesting of transactions using best-effort hardware transactional memory (YL, JWM), pp. 197–206.
TACAS-2008-Malik #verification: Hardware Verification: Techniques, Methodology and Solutions (SM), p. 1.
SAT-2008-DavisTYZ #design #performance #satisfiability: Designing an Efficient Hardware Implication Accelerator for SAT Solving (JDD, ZT, FY, LZ), pp. 48–62.
SIGITE-2007-Hill #forensics: An inexpensive method to shield wireless devices during hardware forensic investigation in a laboratory setting (LWH), pp. 239–244.
AGTIVE-2007-SchosserG #graph grammar #optimisation: Graph Rewriting for Hardware Dependent Program Optimizations (AS, RG), pp. 233–248.
PLDI-2007-SchneiderPG #monitoring #online #optimisation #performance: Online optimizations driven by hardware performance monitoring (FTS, MP, TRG), pp. 373–382.
SAS-2007-BanterleG #abstract domain #implementation #performance: A Fast Implementation of the Octagon Abstract Domain on Graphics Hardware (FB, RG), pp. 315–332.
SAS-2007-Mycroft #analysis #design #evolution #motivation #programming language: Programming Language Design and Analysis Motivated by Hardware Evolution (AM), pp. 18–33.
SAC-2007-ChenL #using: Use of hardware Z-buffered rasterization to accelerate ray tracing (CCC, DSML), pp. 1046–1050.
SAC-2007-YiKOJKD #detection #performance: Memory-efficient content filtering hardware for high-speed intrusion detection systems (SY, BKK, JO, JJ, GK, CRD), pp. 264–269.
COCV-2007-BloemGJPPW: Specify, Compile, Run: Hardware from PSL (RB, SJG, BJ, NP, AP, MW), pp. 3–16.
DAC-2007-GoldgeisserCD #modelling: Modeling Safe Operating Area in Hardware Description Languages (LBG, EC, ZD), pp. 377–382.
DAC-2007-IrvineL #question: Trusted Hardware: Can It Be Trustworthy? (CEI, KNL), pp. 1–4.
DAC-2007-MaoW #embedded: Hardware Support for Secure Processing in Embedded Systems (SM, TW), pp. 483–488.
DATE-2007-AlhoHHH #design: Compact hardware design of Whirlpool hashing core (TA, PH, MH, TDH), pp. 1247–1252.
DATE-2007-BloemGJPPW #automation #case study #interactive #specification #synthesis: Interactive presentation: Automatic hardware synthesis from specifications: a case study (RB, SJG, BJ, NP, AP, MW), pp. 1188–1193.
DATE-2007-ClausZMS #configuration management #using #video: Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system (CC, JZ, FHM, WS), pp. 498–503.
DATE-2007-LinFYL #design #encryption: Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware (KJL, SCF, SHY, CCL), pp. 1265–1270.
DATE-2007-ManetMTCMGLAGLB #configuration management #interactive #programmable: Interactive presentation: RECOPS: reconfiguring programmable devices for military hardware electronics (PM, DM, LT, MDC, OM, YG, JDL, DA, CG, RL, VLB), pp. 994–999.
DATE-2007-MavroidisP #performance #synthesis: Efficient testbench code synthesis for a hardware emulator system (IM, IP), pp. 888–893.
DATE-2007-MossNFFBA #performance #simulation: Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support (LM, MdN, LF, SF, GB, EMA), pp. 876–881.
DATE-2007-NaculRL #architecture #scheduling: Hardware scheduling support in SMP architectures (ACN, FR, ML), pp. 642–647.
DATE-2007-PeterLP #encryption #flexibility #reduction: Flexible hardware reduction for elliptic curve cryptography in GF(2m) (SP, PL, KP), pp. 1259–1264.
DATE-2007-SahinH #algorithm #architecture #interactive #performance #predict: Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm (ES, IH), pp. 183–188.
HPCA-2007-ClarkHYMF #lightweight #using: Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping (NC, AH, SY, SAM, KF), pp. 216–227.
HPCA-2007-SrinathMKP #feedback #performance: Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers (SS, OM, HK, YNP), pp. 63–74.
HPCA-2007-YenBMMVHSW #memory management #named #transaction: LogTM-SE: Decoupling Hardware Transactional Memory from Caches (LY, JB, MRM, KEM, HV, MDH, MMS, DAW), pp. 261–272.
PDP-2007-CilardoCMR #delivery #programmable #security #web #web service: Combining Programmable Hardware and Web Services Technologies for Delivering High-Performance and Interoperable Security (AC, LC, AM, LR), pp. 381–386.
SOSP-2007-RossbachHPRAW #memory management #named #operating system #transaction #using: TxLinux: using and managing hardware transactional memory in an operating system (CJR, OSH, DEP, HER, BA, EW), pp. 87–102.
WRLA-2006-KatelmanM07 #analysis #co-evolution #design #semantics: A Rewriting Semantics for ABEL with Applications to Hardware/Software Co-Design and Analysis (MK, JM), pp. 47–60.
SFM-2006-BombieriFP #design #simulation #verification: Hardware Design and Simulation for Verification (NB, FF, GP), pp. 1–29.
SFM-2006-CabodiM #verification: BDD-Based Hardware Verification (GC, MM), pp. 78–107.
SFM-2006-GuptaGW #satisfiability #verification: SAT-Based Verification Methods and Applications in Hardware Verification (AG, MKG, CW), pp. 108–143.
ICPR-v2-2006-Maruyama #clustering #configuration management #image #realtime: Real-time K-Means Clustering for Color Images on Reconfigurable Hardware (TM), pp. 816–819.
SAC-2006-GacMD #2d #3d #framework #platform: Hardware/software 2D-3D backprojection on a SoPC platform (NG, SM, MD), pp. 222–228.
ASPLOS-2006-AdamsA #comparison: A comparison of software and hardware techniques for x86 virtualization (KA, OA), pp. 2–13.
ASPLOS-2006-ChakrabortyWS #migration #on the fly: Computation spreading: employing hardware migration to specialize CMP cores on-the-fly (KC, PMW, GSS), pp. 283–292.
DAC-2006-PillSCRBC #analysis #formal method #requirements: Formal analysis of hardware requirements (IP, SS, RC, MR, RB, AC), pp. 821–826.
DATE-2006-LinHF #interface: Cooptimization of interface hardware and software for I/O controllers (KJL, SHH, SCF), pp. 724–725.
DATE-2006-LiuBCLM #architecture #performance: Hardware efficient architectures for Eigenvalue computation (YL, CSB, PYKC, PHWL, SJM), pp. 953–958.
DATE-2006-MonchieroPSV #optimisation #performance: Power/performance hardware optimization for synchronization intensive applications in MPSoCs (MM, GP, CS, OV), pp. 606–611.
DATE-2006-PanditKMP #higher-order #synthesis: High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count (SP, SK, CAM, AP), pp. 1203–1204.
DATE-2006-ScharwachterHLAM #interprocedural #multi #network #optimisation #thread #using: An interprocedural code optimization technique for network processors using hardware multi-threading support (HS, MH, RL, GA, HM), pp. 919–924.
DATE-2006-SchaumontSV #design #semantics: Design with race-free hardware semantics (PS, SKS, IV), pp. 571–576.
ISMM-2006-Meyer: A true hardware read barrier (MM), pp. 3–16.
LCTES-2006-DanneP #configuration management #scheduling: An EDF schedulability test for periodic tasks on reconfigurable hardware devices (KD, MP), pp. 93–102.
LCTES-2006-Martonosi #case study #deployment #embedded #experience: Embedded systems in the wild: ZebraNet software, hardware, and deployment experiences (MM), p. 1.
PPoPP-2006-MaratheM #automation: Hardware profile-guided automatic page placement for ccNUMA systems (JM, FM), pp. 90–99.
ICDAR-2005-ZaidiRM #design #online #recognition #using: Hardware Design of On-Line Jawi Character Recognition Chip using Discrete Wavelet Transform (RZ, SR, MY), pp. 91–95.
ITiCSE-2005-CasadoWM #education #network: Teaching networking hardware (MC, GW, NM), pp. 208–212.
ITiCSE-2005-GoldweberDM: The Kaya OS project and the muMPS hardware emulator (MG, RD, MM), pp. 49–53.
IFM-2005-SalaunS #algebra #process #standard: Translating Hardware Process Algebras into Standard Process Algebras: Illustration with CHP and LOTOS (GS, WS), pp. 287–306.
DiGRA-2005-JornmarkAE #evolution #game studies #industrial #ll: Wherever Hardware, There'll be Games. The evolution of hardware and shifting industrial leadership in the gaming industry 1968-2004 (JJ, ASA, ME).
CGO-2005-VaswaniTS #profiling #programmable: A Programmable Hardware Path Profiler (KV, MJT, YNS), pp. 217–228.
DAC-2005-HangalCNC #automation #design #invariant #named: IODINE: a tool to automatically infer dynamic invariants for hardware designs (SH, NC, SN, SC), pp. 775–778.
DAC-2005-NedevschiPB #low cost #power management #recognition #speech #user interface: Hardware speech recognition for user interfaces in low cost, low power devices (SN, RKP, EAB), pp. 684–689.
DATE-2005-CoburnRR #estimation: Hardware Accelerated Power Estimation (JC, SR, AR), pp. 528–529.
DATE-2005-DykaL #encryption #implementation #performance: Area Efficient Hardware Implementation of Elliptic Curve Cryptography by Iteratively Applying Karatsuba’s Method (ZD, PL), pp. 70–75.
DATE-2005-Edwards #challenge #synthesis: The Challenges of Hardware Synthesis from C-Like Languages (SAE), pp. 66–67.
DATE-2005-ElbazTSGABBR #encryption #overview: Hardware Engines for Bus Encryption: A Survey of Existing Techniques (RE, LT, GS, PG, CA, MB, CB, JBR), pp. 40–45.
DATE-2005-FahmyCL #detection #markov: Hardware Acceleration of Hidden Markov Model Decoding for Person Detection (SAF, PYKC, WL), pp. 8–13.
DATE-2005-FrancescoAM #architecture #distributed #flexibility #memory management #message passing: Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture (FP, AP, PM), pp. 736–741.
DATE-2005-FummiLMMPP #prototype: Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation (FF, ML, SM, MM, GP, MP), pp. 798–803.
DATE-2005-KavvadiasN #embedded: Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications (NK, SN), pp. 1060–1061.
DATE-2005-LeeCALK #predict #transaction: A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation (JGL, MKC, KYA, SHL, CMK), pp. 384–389.
DATE-2005-LyseckyV #case study #clustering #using: A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning (RLL, FV), pp. 18–23.
DATE-2005-MarkovM #encryption #logic: Uniformly-Switching Logic for Cryptographic Hardware (ILM, DM), pp. 432–433.
DATE-2005-NolletMAM #configuration management #resource management #runtime: Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles (VN, TM, PA, JYM), pp. 234–239.
DATE-2005-PanainteBV #scheduling: Instruction Scheduling for Dynamic Hardware Configurations (EMP, KB, SV), pp. 100–105.
DATE-2005-RaabeBAZ #architecture #detection #simulation: Hardware Accelerated Collision Detection — An Architecture and Simulation Results (AR, BB, JKA, GZ), pp. 130–135.
DATE-2005-ResanoMC #configuration management #heuristic #hybrid #runtime #scheduling: A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware (JR, DM, FC), pp. 106–111.
DATE-2005-RinconMBL #design pattern #reuse: Model Reuse through Hardware Design Patterns (FR, FM, JB, JCL), pp. 324–329.
DATE-2005-SchattkowskyMR #approach #configuration management #execution #modelling #specification: A Model-Based Approach for Executable Specifications on Reconfigurable Hardware (TS, WM, AR), pp. 692–697.
DATE-2005-TakachBB #c #design: C Based Hardware Design for Wireless Applications (AT, BB, TB), pp. 124–129.
LCTES-2005-Oi #design #java #on the #virtual machine: On the design of the local variable cache in a hardware translation-based java virtual machine (HO), pp. 87–94.
PDP-2005-PetitSP #comparison #protocol: A Comparison Study of the HLRC-DU Protocol versus a HLRC Hardware Assisted Protocol (SP, JS, AP), pp. 197–204.
PPoPP-2005-Hanrahan #performance #question #why: Why is graphics hardware so fast? (PH), p. 1.
VLDB-2004-Ailamaki #architecture #database: Database Architecture for New Hardware (AA), p. 1241.
VLDB-2004-BandiSAA #case study #database: Hardware Acceleration in Commercial Databases: A Case Study of Spatial Operations (NB, CS, AEA, DA), pp. 1021–1032.
WCRE-2004-RocheC #comprehension #reverse engineering: Combined Software and Hardware Comprehension in Reverse Engineering (PLR, AC), pp. 234–243.
IFM-2004-PuHHY #approach #clustering: An Optimal Approach to Hardware/Software Partitioning for Synchronous Model (GP, DVH, JH, WY), pp. 363–381.
SEFM-2004-GeguangXSZHY #approach #clustering #multi: An Approach to Hardware/Software Partitioning for Multiple Hardware Devices Model (GP, XZ, SW, ZQ, JH, WY), pp. 376–385.
SEFM-2004-NaiyongJ #co-evolution #design #modelling #specification: Resource Models and Pre-Compiler Specification for Hardware/Software Co-Design Language (NJ, JH), pp. 132–141.
ICPR-v1-2004-WoetzelK #estimation #multi #realtime: Multi-Camera Real-Time Depth Estimation with Discontinuity Handling on PC Graphics Hardware (JW, RK), pp. 741–744.
PLDI-2004-Adl-TabatabaiHSS #metadata #monitoring: Prefetch inection based on hardware monitoring and object metadata (ARAT, RLH, MJS, SS), pp. 267–276.
SAC-2004-MortonL #design #kernel: A hardware/software kernel for system on chip designs (AM, WML), pp. 869–875.
SAC-2004-PanagopoulosPP #attribute grammar: A hardware extension of the RISC microprocessor for Attribute Grammar evaluation (IP, CP, GKP), pp. 897–904.
ASPLOS-2004-CherHV #analysis #garbage collection: Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign (CYC, ALH, TNV), pp. 199–210.
DAC-2004-FrancescoMABCM #approach #runtime: An integrated hardware/software approach for run-time scratchpad management (FP, PM, DA, LB, FC, JMM), pp. 238–243.
DAC-2004-KimYKK #functional #performance #simulation: Communication-efficient hardware acceleration for fast functional simulation (YIK, WSY, YSK, CMK), pp. 293–298.
DAC-2004-NakamuraHKYY #c #c++ #communication #performance #using: A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication (YN, KH, IK, KY, TY), pp. 299–304.
DAC-2004-ResanoM #configuration management #scheduling: Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware (JR, DM), pp. 119–124.
DAC-2004-VermeulenUG #automation #debugging #generative: Automatic generation of breakpoint hardware for silicon debug (BV, MZU, SKG), pp. 514–517.
DATE-DF-2004-BannowH #design #evaluation #object-oriented: Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications (NB, KH), pp. 268–273.
DATE-DF-2004-CilardoMRS #composition #configuration management: Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware (AC, AM, LR, GPS), pp. 206–211.
DATE-v1-2004-LyseckyV #architecture #clustering #configuration management #logic: A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning (RLL, FV), pp. 480–485.
DATE-v1-2004-WolffPM: Test Compression and Hardware Decompression for Scan-Based SoCs (FGW, CAP, DRM), pp. 716–717.
DATE-v1-2004-ZambrenoCSN #flexibility #using: Flexible Software Protection Using Hardware/Software Codesign Techniques (JZ, ANC, RS, BN), pp. 636–641.
DATE-v2-2004-GuilleyHMPP: CMOS Structures Suitable for Secured Hardware (SG, PH, YM, RP, JP), pp. 1414–1415.
DATE-v2-2004-WangLC #fault #hybrid #testing: Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets (SW, XL, STC), pp. 1296–1301.
HPCA-2004-AamodtCHWS: Hardware Support for Prescient Instruction Prefetch (TMA, PC, PH, HW, JPS), pp. 84–95.
LCTES-2004-GuoBN #compilation #configuration management #reuse: Input data reuse in compiling window operations onto reconfigurable hardware (ZG, BB, WAN), pp. 249–256.
DATE-2005-UllmannJB04 #configuration management: Hardware Support for QoS-based Function Allocation in Reconfigurable Systems (MU, WJ, JB), pp. 259–264.
SIGMOD-2003-SunAA: Hardware Acceleration for Spatial Selections and Joins (CS, DA, AEA), pp. 455–466.
ICSM-2003-ForbesB #deployment #process: Improving Hardware, Software, and Training Deployment Processes (JAF, ERB), pp. 377–380.
FME-2003-QinC: Mapping Statecharts to Verilog for Hardware/Software Co-specification (SQ, WNC), pp. 282–300.
CHI-2003-FriedmanKH #online #what: Hardware companions?: what online AIBO discussion forums reveal about the human-robotic relationship (BF, PHKJ, JH), pp. 273–280.
SIGIR-2003-AgunF #component #named: HAT: a hardware assisted TOP-DOC inverted index component (SKA, OF), pp. 447–448.
SAC-2003-ScerriMST #algorithm #case study #constraints #distributed #multi: Are Multiagent Algorithms Relevant for Real Hardware? A Case Study of Distributed Constraint Algorithms (PS, PJM, WMS, MT), pp. 38–44.
SAC-2003-Wainer #interactive #standard #using #visualisation: Interactive Computation and Visualization of Fetch Using Standard Computer Graphics Hardware (MW), pp. 961–965.
GPCE-2003-Kastner #analysis #named #optimisation: TDL: A Hardware Description Language for Retargetable Postpass Optimizations and Analyses (DK), pp. 18–36.
CGO-2003-ChenHC #monitoring #performance #using: Dynamic Trace Selection Using Performance Monitoring Hardware Sampling (HC, WCH, DyC), pp. 79–90.
DAC-2003-DamaseviciusMS #design pattern: Application of design patterns for hardware design (RD, GM, VS), pp. 48–53.
DAC-2003-LekatsasHCJS #agile #framework #named #platform #prototype: CoCo: a hardware/software platform for rapid prototyping of code compression technologies (HL, JH, STC, VJ, MS), pp. 306–311.
DAC-2003-StittLV #approach #clustering: Dynamic hardware/software partitioning: a first approach (GS, RLL, FV), pp. 250–255.
DATE-2003-BesanaB #automation #case study #code generation #design #framework #platform: Application Mapping to a Hardware Platform through Automated Code Generation Targeting a RTOS: A Design Case Study (MB, MB), pp. 20041–20044.
DATE-2003-Castro-LopezFMR #behaviour #modelling #simulation #using: Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages (RCL, FVF, FM, ÁRV), pp. 10168–10175.
DATE-2003-IndrusiakLRG #configuration management #implementation #ubiquitous: Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues (LSI, FL, RAdLR, MG), pp. 10940–10945.
DATE-2003-LangeK #configuration management #design #embedded #framework #platform: Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems (SL, UK), pp. 10302–10309.
DATE-2003-MolinaMH: High-Level Allocation to Minimize Internal Hardware Wastage (MCM, JMM, RH), pp. 10264–10269.
DATE-2003-Mooney #clustering #operating system: Hardware/Software Partitioning of Operating Systems (VJM), pp. 10338–10339.
DATE-2003-Pirola #memory management: A Solution for Hardware Emulation of Non Volatile Memory Macrocells (AP), pp. 20262–20267.
DATE-2003-RosaLP #configuration management #design: Hardware/Software Design Space Exploration for a Reconfigurable Processor (ALR, LL, CP), pp. 10570–10575.
DATE-2003-YooBBPJ #abstraction #modelling #performance #simulation: Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer (SY, IB, AB, YP, AAJ), pp. 10550–10555.
DATE-2003-YooJ #abstraction: Introduction to Hardware Abstraction Layers for SoC (SY, AAJ), pp. 10336–10337.
LCTES-2003-SureshNVVS #clustering #embedded #profiling #tool support: Profiling tools for hardware/software partitioning of embedded applications (DCS, WAN, FV, JRV, GS), pp. 189–198.
PDP-2003-LeePK #adaptation #multi: An Adaptive Multi-Module Cache with Hardware Prefetching Mechanism for Multimedia Applications (JHL, GHP, SDK), p. 109–?.
SOSP-2003-LieTH #implementation #operating system: Implementing an untrusted operating system on trusted hardware (DL, CAT, MH), pp. 178–192.
FATES-2003-SungC #embedded #fault #injection #interactive #testing #using: Interaction Testing in an Embedded System Using Hardware Fault Injection and Program Mutation (AS, BC), pp. 192–204.
SAT-2003-ClarkeTVW #abstraction #satisfiability #verification: SAT Based Predicate Abstraction for Hardware Verification (EMC, MT, HV, DW), pp. 78–92.
AdaEurope-2002-WardA #ada #compilation: Language Issues of Compiling Ada to Hardware (MW, NCA), pp. 88–99.
PLDI-2002-SoHD #approach #compilation #design #performance: A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-based Systems (BS, MWH, PCD), pp. 165–176.
ASPLOS-2002-SasankaHA #adaptation #energy: Joint local and global hardware adaptations for energy (RS, CJH, SVA), pp. 144–155.
DAC-2002-CadambiMA #functional #performance #scalability #simulation: A fast, inexpensive and scalable hardware acceleration technique for functional simulation (SC, CM, PA), pp. 570–575.
DAC-2002-HortaLTP #configuration management #plugin #runtime: Dynamic hardware plugins in an FPGA with partial run-time reconfiguration (ELH, JWL, DET, DBP), pp. 343–348.
DAC-2002-LekatsasHJ #design #embedded #performance: Design of an one-cycle decompression hardware for performance increase in embedded systems (HL, JH, VJ), pp. 34–39.
DAC-2002-RaganSS #co-evolution #concurrent #cost analysis #design: A detailed cost model for concurrent use with hardware/software co-design (DR, PS, PS), pp. 269–274.
DAC-2002-SiegmundM #communication #declarative #novel #protocol #specification #synthesis: A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications (RS, DM), pp. 602–607.
DATE-2002-MichelWWM #trade-off: Hardware/Software Trade-Offs for Advanced 3G Channel Coding (HM, AW, NW, MM), pp. 396–401.
DATE-2002-SkliarovaF #configuration management #satisfiability #using: A SAT Solver Using Software and Reconfigurable Hardware (IS, AdBF), p. 1094.
PDP-2002-CorsonelloSST #algorithm #configuration management #implementation #performance: Efficient Implementation of Cellular Algorithms on Reconfigurable Hardware (PC, GS, GS, DT), pp. 211–218.
PDP-2002-PorrmannWKR #configuration management #implementation #network: Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator (MP, UW, HK, UR), p. 243–?.
TestCom-2002-Peleska #integration #product line #testing: Hardware/Software Integration Testing for the new Airbus Aircraft Families (JP), p. 335–?.
FME-2001-SilvaSJ #clustering #parallel #process: Serialising Parallel Processes in a Hardware/Software Partitioning Context (LS, AS, GJ), pp. 344–363.
SAS-2001-SharpM #scheduling: Soft Scheduling for Hardware (RS, AM), pp. 57–72.
DAC-2001-KoushanfarQ: Hardware Metering (FK, GQ), pp. 490–493.
DAC-2001-KuhnOWREK #framework #object-oriented #specification #synthesis #verification: A Framework for Object Oriented Hardware Specification, Verification, and Synthesis (TK, TO, MW, WR, ME, YK), pp. 413–418.
DAC-2001-ReyneriCSL #co-evolution #design #library: A Hardware/Software Co-design Flow and IP Library Based of SimulinkTM (LMR, FC, AS, LL), pp. 593–598.
DAC-2001-WangKMR #set: Hardware/Software Instruction Set Configurability for System-on-Chip Processors (AW, EK, DEM, CR), pp. 184–188.
DATE-2001-AkgulM: System-on-a-chip processor synchronization support in hardware (BSA, VJMI), pp. 633–641.
DATE-2001-NayakHCB #analysis #automation #fault #matlab #precise #synthesis: Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs (AN, MH, ANC, PB), pp. 722–728.
DATE-2001-Parameswaran #performance: Code placement in hardware/software co-synthesis to improve performance and reduce cost (SP), pp. 626–632.
DATE-2001-Wilson #challenge #design: Managing the SoC design challenge with “Soft” hardware (RW), pp. 610–611.
DATE-2001-XieW #graph #scheduling: Allocation and scheduling of conditional task graph in hardware/software co-synthesis (YX, WW), pp. 620–625.
HPCA-2001-AbaliFSPS #in memory #memory management #performance: Performance of Hardware Compressed Main Memory (BA, HF, XS, DEP, TBS), pp. 73–81.
HPCA-2001-DelaluzKVSI #energy #using: DRAM Energy Management Using Software and Hardware Directed Power Mode Control (VD, MTK, NV, AS, MJI), pp. 159–169.
HPCA-2001-FangZCHM #online: Reevaluating Online Superpage Promotion with Hardware Support (ZF, LZ, JBC, WCH, SAM), pp. 63–72.
LCTES-OM-2001-MerillonM #embedded #framework: Dealing with Hardware in Embedded Software: A General Framework Based on the Devil Language (FM, GM), pp. 121–127.
PDP-2001-GarzaranBIV #effectiveness #multi: Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware (MJG, JLB, PEI, VV), pp. 345–354.
TACAS-2001-MycroftS #co-evolution #design #functional #using: Hardware/Software Co-Design Using Functional Languages (AM, RS), pp. 236–251.
IFM-2000-Bowen #animation #logic programming #semantics #specification: Combining Operational Semantics, Logic Programming and Literate Programming in the Specification and Animation of the Verilog Hardware Description Language (JPB), pp. 277–296.
ICFP-2000-Seger #functional #programming #verification: Combining functional programming and hardware verification (CJHS), p. 244.
TOOLS-USA-2000-Pour00a #named #towards: JINI: Towards Seamless Connectivity of Hardware and Software Services [Abstract] (GP), pp. 463–464.
ASPLOS-2000-ConnorsHCH #reuse: Hardware Support for Dynamic Management of Compiler-Directed Computation Reuse (DAC, HCH, BCC, WmWH), pp. 222–233.
ASPLOS-2000-KawahitoKN #effectiveness #null #pointer: Effective Null Pointer Check Elimination Utilizing Hardware Trap (MK, HK, TN), pp. 139–149.
ASPLOS-2000-NandaMSSSS #design #multi #named #programmable #realtime: MemorIES: A Programmable, Real-Time Hardware Emulation Tool for Multiprocessor Server Design (AKN, KKM, KS, RKS, VS, TBS), pp. 37–48.
DAC-2000-BoulisS #configuration management #design: System design of active basestations based on dynamically reconfigurable hardware (AB, MBS), pp. 501–506.
DAC-2000-ChenDSSC #embedded #self: Embedded hardware and software self-testing methodologies for processor cores (LC, SD, PS, KS, YC), pp. 625–630.
DAC-2000-DalpassoBB: Hardware/software IP protection (MD, AB, LB), pp. 593–596.
DAC-2000-EisnerSHNNV #design #protocol: A methodology for formal design of hardware control with application to cache coherence protocols (CE, IS, RH, WGN, KLN, KV), pp. 724–729.
DAC-2000-KatagiriYKHT #communication #concurrent #implementation #multi #protocol: Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization (HK, KY, AK, TH, KT), pp. 762–767.
DAC-2000-PaulPT #modelling #virtual machine: A codesign virtual machine for hierarchical, balanced hardware/software system modeling (JMP, SNP, DET), pp. 390–395.
DATE-2000-CataldoCPW #functional #generative: Optimal Hardware Pattern Generation for Functional BIST (SC, SC, PP, HJW), pp. 292–297.
DATE-2000-HaugKR #design #framework #platform: A Hardware Platform for VLIW Based Emulation of Digital Designs (GH, UK, WR), p. 747.
DATE-2000-SilvaDM #configuration management #correlation #using: Mixed-Signal BIST Using Correlation and Reconfigurable Hardware (JMdS, JSD, JSM), p. 744.
OSDI-2000-MerillonRCMM #named #programming: Devil: An IDL for Hardware Programming (FM, LR, CC, RM, GM), pp. 17–30.
PDP-2000-CastellanoRCS #multi #trade-off: Pipelining-based tradeoffs for hardware/software codesign of multimedia systems (JPC, DCSR, OC, ÁS), pp. 383–390.
FM-v1-1999-LotzKW #security: A Formal Security Model for Microprocessor Hardware (VL, VK, GW), pp. 718–737.
IFM-1999-He #framework: A Common Framework for Mixed Hardware/Software Systems (JH), pp. 3–25.
AdaEurope-1999-LopezVV #ada #design #embedded #using: Hardware/Software Embedded System Specifiaction and Design Using Ada and VHDL (AL, MV, EV), pp. 356–370.
DAC-1999-AbramoviciSS #configuration management #satisfiability #using: A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware (MA, JTdS, DGS), pp. 684–690.
DAC-1999-Harbison #trade-off: System-Level Hardware/Software Trade-offs (SPH), pp. 258–259.
DAC-1999-Henkel #approach #clustering #embedded #power management: A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems (JH), pp. 122–127.
DAC-1999-KocanS #configuration management #fault: Dynamic Fault Diagnosis on Reconfigurable Hardware (FK, DGS), pp. 691–696.
DAC-1999-KuhnRK #java #simulation: Description and Simulation of Hardware/Software Systems with Java (TK, WR, UK), pp. 790–793.
DAC-1999-SchaumontCVEB #behaviour #reuse: Hardware Reuse at the Behavioral Level (PS, RC, SV, ME, IB), pp. 784–789.
DAC-1999-WilkesH #design #interface: Application of High Level Interface-Based Design to Telecommunications System Hardware (DW, MMKH), pp. 778–783.
DAC-1999-ZhuL #compilation #configuration management: Hardware Compilation for FPGA-Based Configurable Computing Machines (XZ, BL), pp. 697–702.
DATE-1999-Dav #configuration management #distributed #embedded #named #realtime: CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems (BPD), pp. 97–104.
DATE-1999-FleischmannBK #component #configuration management #embedded #java: Codesign of Embedded Systems Based on Java and Reconfigurable Hardware Components (JF, KB, RK), pp. 768–769.
DATE-1999-GhoshKL #c #c++ #synthesis: Hardware Synthesis from C/C++ (AG, JK, SYL), pp. 387–389.
DATE-1999-MaestroMH #approach #problem: The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach (JAM, DM, RH), pp. 766–767.
DATE-1999-Micheli #c #c++ #modelling #synthesis: Hardware Synthesis from C/C++ Models (GDM), pp. 382–383.
DATE-1999-NicoliciA #performance: Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths (NN, BMAH), p. 289–?.
DATE-1999-RadetzkiSPN #analysis #data type #modelling #object-oriented #synthesis: Data Type Analysis for Hardware Synthesis from Object-Oriented Models (MR, AS, WPR, WN), p. 491–?.
DATE-1999-VercauterenSV #constraints #generative #interface #realtime #synthesis: Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time Constraints (SV, JvdS, DV), pp. 556–561.
HPCA-1999-TanakaMH #distributed #lightweight #memory management: Lightweight Hardware Distributed Shared Memory Supported by Generalized Combining (KT, TM, KH), pp. 90–99.
HPCA-1999-ZhangRT #parallel: Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors (YZ, LR, JT), pp. 135–139.
TACAS-1999-KahloucheVZ #communication #consistency #protocol #testing #using: Hardware Testing Using a Communication Protocol Conformance Testing Tool (HK, CV, MZ), pp. 315–329.
TACAS-1999-KernOG #framework #verification: A Light-Weight Framework for Hardware Verification (CK, TOT, MRG), pp. 330–344.
CAV-1999-Dill #verification: Alternative Approaches to Hardware Verification (DLD), p. 1.
IWTCS-1999-HeT #testing: Protocol-Inspired Hardware Testing (JH, KJT), pp. 131–148.
ICFP-1998-BjesseCSS #design #haskell #named: Lava: Hardware Design in Haskell (PB, KC, MS, SS), pp. 174–184.
SIGAda-1998-MillsP #ada #analysis #co-evolution #design #migration: Hardware/Software Co-Design: VHDL and Ada 95 Code Migration and Integrated Analysis (MM, GP), pp. 18–27.
SIGAda-1998-WongL #ada #design #kernel: Kernel Ada to Unify Hardware and Software Design (SW, GL), pp. 28–38.
DAC-1998-SmithM #automation #component #composition: Automated Composition of Hardware Components (JS, GDM), pp. 14–19.
DATE-1998-GrodeKM #clustering #resource management: Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System (JG, PVK, JM), pp. 22–27.
DATE-1998-MaestroMM #clustering #estimation #parallel #process: A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process (JAM, DM, HM), pp. 218–225.
DATE-1998-NiemannM #communication #concurrent #synthesis: Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems (RN, PM), pp. 912–913.
DATE-1998-ObergHK #communication #grammarware #protocol #scheduling #synthesis: Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols (JÖ, AH, AK), pp. 596–603.
DATE-1998-PostMG #design: A System-Level Co-Verification Environment for ATM Hardware Design (GP, AM, TG), pp. 424–428.
DATE-1998-ReetzSK #specification #verification: Formal Specification in VHDL for Hardware Verification (RR, KS, TK), pp. 257–263.
DATE-1998-SalapuraG #co-evolution #design #fuzzy: Hardware/Software Co-Design of a Fuzzy RISC Processor (VS, MG), pp. 875–882.
DATE-1998-SchneiderKHD #algorithm #architecture #comparison: From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms (CS, MK, TH, JD), pp. 186–190.
DATE-1998-SchumacherN #modelling #object-oriented #parallel: Object-Oriented Modelling of Parallel Hardware Systems (GS, WN), pp. 234–241.
DATE-1998-SrinivasanRV #clustering #design: Hardware Software Partitioning with Integrated Hardware Design Space Exploration (VS, SR, RV), pp. 28–35.
DATE-1998-SungH: Optimized Timed Hardware Software Cosimulation without Roll-back (WS, SH), pp. 945–946.
HPCA-1998-ZhangRT #distributed #parallel #runtime: Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors (YZ, LR, JT), pp. 162–173.
FME-1997-SilvaSB #clustering #normalisation #reduction: A Normal Form Reduction Strategy for Hardware/Software Partitioning (LS, AS, EB), pp. 624–643.
HCI-SEC-1997-Breinholt #interface #prototype: Software Prototyping of Hardware Interfaces (GB), pp. 585–588.
PLDI-1997-AmmonsBL #performance #profiling: Exploiting Hardware Performance Counters with Flow and Context Sensitive Profiling (GA, TB, JRL), pp. 85–96.
ASE-1997-DevanbuS #automation #research #using #verification: Research Directions for Automated Software Verification: Using Trusted Hardware (PTD, SGS), pp. 274–279.
DAC-1997-BakshiG #clustering #pipes and filters: Hardware/Software Partitioning and Pipelining (SB, DG), pp. 713–716.
DAC-1997-BauerE #approach: Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach (MB, WE), pp. 774–779.
DAC-1997-HartoogRRDDHK #generative #tool support: Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign (MRH, JAR, PDR, SD, DDD, EAH, NK), pp. 303–306.
DAC-1997-HenkelE #using: A Hardware/Software Partitioner Using a Dynamically Determined Granularity (JH, RE), pp. 691–696.
DAC-1997-LiaoTG #design #implementation #modelling #performance: An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment (SYL, SWKT, RKG), pp. 70–75.
DAC-1997-PasseroneLCS #analysis #performance #prototype #trade-off: Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis (CP, LL, MC, ALSV), pp. 389–394.
EDTC-1997-MirandaKCM #architecture #generative #optimisation: Architectural exploration and optimization for counter based hardware address generation (MM, MK, FC, HDM), pp. 293–298.
EDTC-1997-RomanowiczLLRABMP #modelling #simulation #transducer #using: Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language (BR, ML, PL, PR, HPA, AB, VM, FP), pp. 119–123.
EDTC-1997-Schneider #abstraction #architecture #trade-off: A methodology for hardware architecture trade-off at different levels of abstraction (CS), pp. 537–541.
TACAS-1997-Berry #optimisation #source code #synthesis #verification: Hardware and Software Synthesis, Optimization, and Verification from Esterel Programs (GB), pp. 1–3.
CAV-1997-McMillan #composition #design #refinement: A Compositional Rule for Hardware Design Refinement (KLM), pp. 24–35.
DAC-1996-AdamsT #design: The Design of Mixed Hardware/Software Systems (JKA, DET), pp. 515–520.
DAC-1996-BinhISH #algorithm #clustering #design #pipes and filters: A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts (NNB, MI, AS, NH), pp. 527–532.
DAC-1996-GanapathyNJFWN #functional #verification: Hardware Emulation for Functional Verification of K5 (GG, RN, GJ, DF, MW, JN), pp. 315–318.
DAC-1996-Lin #design #network: A System Design Methodology for Software/Hardware Co-Development of Telecommunication Network Applications (BL), pp. 672–677.
DAC-1996-SchnaiderY #development #simulation: Software Development in a Hardware Simulation Environment (BS, EY), pp. 684–689.
DAC-1996-SuzukiS #estimation #performance: Efficient Software Performance Estimation Methods for Hardware/Software Codesign (KS, ALSV), pp. 605–610.
HPCA-1996-GovindarajanAG #pipes and filters: Co-Scheduling Hardware and Software Pipelines (RG, ERA, GRG), pp. 52–61.
ICDAR-v2-1995-KimLK #architecture #array #implementation #parallel #recognition: Parallel hardware implementation of handwritten character recognition system on wavefront array processor architecture (YJK, SWL, MWK), pp. 715–718.
CHI-1995-PiernotFSMY #design #interface: Designing the PenPal: Blending Hardware and Software in a User-Interface for Children (PP, RMF, RS, JM, MPY), pp. 511–518.
ECOOP-1995-HolzleU #object-oriented #question: Do Object-Oriented Languages Need Special Hardware Support? (UH, DU), pp. 283–302.
DAC-1995-BormannLPV #design #industrial #model checking: Model Checking in Industrial Hardware Design (JB, JL, MP, GV), pp. 298–303.
DAC-1995-SilburtPBNDW #behaviour #concurrent #design #modelling #simulation: Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation (AS, IP, JB, SN, MD, GW), pp. 528–533.
CAV-1995-BasinK #higher-order #logic #monad #using #verification: Hardware Verification using Monadic Second-Order Logic (DAB, NK), pp. 31–41.
CAV-1995-HojatiB #abstraction #automation: Automatic Datapath Abstraction In Hardware Systems (RH, RKB), pp. 98–113.
LICS-1995-Tronci #functional #logic programming #verification: Hardware Verification, Boolean Logic Programming, Boolean Functional Programming (ET), pp. 408–418.
SAC-1994-RondogiannisW #data flow #higher-order #implementation: Higher-order dataflow and its implementation on stock hardware (PR, WWW), pp. 431–435.
ASPLOS-1994-CarterKD #performance: Hardware Support for Fast Capability-based Addressing (NPC, SWK, WJD), pp. 319–327.
ASPLOS-1994-ThekkathE #effectiveness #multi: The Effectiveness of Multiple Hardware Contexts (RT, SJE), pp. 328–337.
ASPLOS-1994-ThekkathL #exception #performance: Hardware and Software Support for Efficient Exception Handling (CAT, HML), pp. 110–119.
DAC-1994-KalavadeeL #co-evolution #design: Manifestations of Heterogeneity in Hardware/Software Co-Design (AK, EAL), pp. 437–438.
DAC-1994-Radtke #design #process #scalability: The AT&T 5ESS Hardware Design Environment: A Large System’s Hardware design Process (KAR), pp. 527–531.
DAC-1994-Rowson: Hardware/Software Co-Simulation (JAR), pp. 439–440.
EDAC-1994-EdwardsF #development #embedded: A Development Environment for the Cosynthesis of Embedded Software/Hardware Systems (ME, JF), pp. 469–473.
EDAC-1994-GrantML #generative #optimisation: Optimization of Address Generator Hardware (DMG, JLvM, PERL), pp. 325–329.
CAV-1994-BeerBGGY #verification: Methodology and System for Practical Formal Verification of Reactive Hardware (IB, SBD, DG, RG, MY), pp. 182–193.
CAV-1994-CyrlukN #logic #verification: Ground Temporal Logic: A Logic for Hardware Verification (DC, PN), pp. 247–259.
CAV-1994-Schubert #hybrid #reasoning: A Hybrid Model for Reasoning about Composed Hardware Systems (ETS), pp. 260–272.
CAV-1994-ZhuS: The Completeness of a Hardware Inference System (ZZ, CJHS), pp. 286–298.
ICLP-1994-BreuerSK #design #proving: Proving Hardware Designs (PTB, LS, CDK), p. 745.
SIGMOD-1993-FushimiK #database #named #pipes and filters: GREO: A Commercial Database Processor Based on A Pipelined Hardware Sorter (SF, MK), pp. 449–452.
FPCA-1993-Feeley: Polling Efficiently on Stock Hardware (MF), pp. 179–190.
INTERCHI-1993-Wenzel #design #interface #performance: Perceptual vs. hardware performance in advanced acoustic interface design (EMW), pp. 363–366.
DAC-1993-Kra #co-evolution #design: A Cross-Debugging Method for Hardware/Software Co-design Environments (YK), pp. 673–677.
HPDC-1993-Coddington #analysis #distributed #physics: An Analysis of Distributed Computing Software and Hardware for Applications in Computational Physics (PDC), pp. 179–186.
PDP-1993-WuWF #approach #fault tolerance: A uniform approach to software and hardware fault tolerance (JW, YMW, EBF), pp. 409–416.
STOC-1993-BorodinRSU #how #question: How much can hardware help routing? (AB, PR, BS, EU), pp. 573–582.
TRI-Ada-C-1992-HummerB #ada #design #safety: When Hardware Becomes Software: Designing a Safety-Critical System with Ada (JH, LB), pp. 538–544.
ASPLOS-1992-HillLRW #memory management #multi #scalability: Cooperative Shared Memory: Software and Hardware Support for Scalable Multiprocesors (MDH, JRL, SKR, DAW), pp. 262–273.
DAC-1992-BeckerST: An Engineering Environment for Hardware/Software Co-Simulation (DB, RKS, SGT), pp. 129–134.
DAC-1992-GuptaCM #component #simulation #synthesis: Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components (RKG, CJNCJ, GDM), pp. 225–230.
ICSE-1991-FrankeP #perspective: Hardware/Software Codesign: A Perspective (DWF, MKP), pp. 344–352.
ASPLOS-1991-BhandarkarC #architecture #performance: Performance From Architecture: Comparing a RISC and CISC with Similar Hardware Organization (DB, DWC), pp. 310–319.
ASPLOS-1991-CullerSSEW #automaton #parallel #thread: Fine-Grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine (DEC, AS, KES, TvE, JW), pp. 164–175.
DAC-1991-BryantBS #evaluation #verification: Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation (REB, DLB, CJHS), pp. 397–402.
DAC-1991-BuschV #design: Proof-Aided Design of Verified Hardware (HB, GV), pp. 391–396.
DAC-1991-Hafer #constraints #synthesis: Constraint improvements for MILP-based hardware synthesis (LJH), pp. 14–19.
DAC-1991-JainB #simulation: Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators (AJ, REB), pp. 219–222.
CAV-1991-SchneiderKK #automation #proving: Automating Most Parts of Hardware Proofs in HOL (KS, RK, TK), pp. 365–375.
DAC-1990-IshiuraYY #behaviour #design #named #semantics: NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I (NI, HY, SY), pp. 8–13.
DAC-1990-SatoKO #implementation #memory management: A Hardware Implementation of Gridless Routing Based on Content Addressable Memory (MS, KK, TO), pp. 646–649.
DAC-1990-ScheichenzuberGLM #behaviour #data flow #synthesis: Global Hardware Synthesis from Behavioral Dataflow Descriptions (JS, WG, UL, SM), pp. 456–461.
CAV-1990-Eveking #automation #verification: Automatic Verification of Extensions of Hardware Descriptions (HE), pp. 2–12.
CAV-1990-Pixley #equivalence #implementation: Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence (CP), pp. 54–64.
DAC-1989-AgrawalTD #algorithm #logic: Algorithms for Accuracy Enhancement in a Hardware Logic Simulator (PA, RT, WJD), pp. 645–648.
DAC-1989-George #modelling #simulation: Evaluating Hardware Models in DIGITAL’s System Simulation Environment (AKG), pp. 642–644.
DAC-1989-Norrod #algorithm #automation #generative #testing: An Automatic Test Generation Algorithm for Hardware Description Languages (FEN), pp. 429–434.
DAC-1989-NowakM #code generation #verification: Verification of Hardware Descriptions by Retargetable Code Generation (LN, PM), pp. 441–447.
DAC-1989-YasuuraI #design #semantics #standard: Semantics of a Hardware Design Language for Japanese Standardization (HY, NI), pp. 836–839.
LFP-1988-Norman #combinator #performance #reduction #using: Faster Combinator Reduction Using stock Hardware (ACN), pp. 235–243.
OOPSLA-1988-Rose #performance: Fast Dispatch Mechanisms for Stock Hardware (JRR), pp. 27–35.
PLDI-1988-KeutzerW #compilation: Anatomy of a Hardware Compiler (KK, WW), pp. 95–104.
ICSE-1988-Wasserman #development: Implications of Hardware Advances for Software Development (AIW), pp. 250–253.
DAC-1988-DrongowskiBRIW #design #visual notation: A Graphical Hardware Design Language (PJD, JRB, RR, SI, THW), pp. 108–114.
DAC-1988-Hansen #compilation #logic #simulation: Hardware Logic Simulation by Compilation (CH), pp. 712–716.
DAC-1988-KimTH #automation #using: Automatic Insertion of BIST Hardware Using VHDL (KK, JGT, DSH), pp. 9–15.
DAC-1988-Lewis #programmable #simulation: A Programmable Hardware Accelerator for Compiled Electrical Simulation (DML), pp. 172–177.
DAC-1988-StavridouBE #case study #comparative #specification #verification: Formal Specification and Verification of Hardware: A Comparative Case Study (VS, HB, DAE), pp. 197–204.
FPCA-1987-NorthR #concurrent #garbage collection: Concurrent garbage collection on stock hardware (SCN, JHR), pp. 113–133.
ICSE-1987-Matsumoto #case study #experience: Ten Years Experiences of a Software/Hardware Producing Environment (YM), p. 291.
ICSE-1987-Roman #distributed #interactive #specification: Specifying Software/Hardware Interactions in Distributed Systems (GCR), pp. 126–141.
ASPLOS-1987-CargillL #debugging #profiling: Cheap Hardware Support for Software Debugging and Profiling (TAC, BNL), pp. 82–83.
ASPLOS-1987-SteenkisteH #lisp #type checking: Tags and Type Checking in Lisp: Hardware and Software Approaches (PS, JLH), pp. 50–59.
ASPLOS-1987-Wirth #architecture #programming language: Hardware Architectures for Programming Languages and Programming Languages for Hardware Architectures (NW), pp. 2–8.
DAC-1987-AgrawalDEFJK #architecture #design: Architecture and Design of the MARS Hardware Accelerator (PA, WJD, AKE, WCF, HVJ, ASK), pp. 101–107.
DAC-1987-ChandrasekharPC #design #term rewriting #verification: Application of Term Rewriting Techniques to Hardware Design Verification (MSC, JPP, KWC), pp. 277–282.
DAC-1987-LeungS #concept #design #framework: A Conceptual Framework for Designing ASIC Hardware (SSL, MAS), pp. 592–595.
DAC-1987-Smith #scalability: A Hardware Switch Level Simulator for Large MOS Circuits (MTS), pp. 95–100.
DAC-1987-VladimirescuWKBKDNJL #simulation: A Vector Hardware Accelerator with Circuit Simulation Emphasis (AV, DW, MK, ZB, AK, KD, KCN, NJ, SL), pp. 89–94.
DAC-1987-WonSE: A Hardware Accelerator for Maze Routing (YW, SS, YMEZ), pp. 800–806.
SLP-1987-BushCMD87 #experience #prolog #specification: Experience with Prolog as a Hardware Specification Language (WRB, GC, PCM, AMD), pp. 490–498.
SLP-1987-NakashimaN87 #architecture: Hardware Architecture of the Sequential Inference Machine: PSI-II (HN, KN), pp. 104–113.
DAC-1986-McFarland #behaviour #bottom-up #design #synthesis #using: Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions (MCM), pp. 474–480.
DAC-1986-TakasakiSNIK #logic #simulation: HAL II: a mixed level hardware logic simulation system (ST, TS, NN, HI, NK), pp. 581–587.
DAC-1986-WatanabeS #algorithm #implementation: A new routing algorithm and its hardware implementation (TW, YS), pp. 574–580.
SIGMOD-1985-Robinson #performance: A Fast General-Purpose Hardware Synchronisation Mechanism (JTR), pp. 122–130.
FPCA-1985-PatelSE85 #algorithm #analysis #multi #named #specification #synthesis: vFP: An Environment for the Multi-level Specification, Analysis, and Synthesis of Hardware Algorithms (DP, MDFS, MDE), pp. 238–255.
DAC-1985-Lewis #simulation: A hardware engine for analogue mode simulation of MOS digital circuits (DML), pp. 345–351.
DAC-1985-SmithFC #architecture #assessment #design: An architecture design and assessment system for software/hardware codesign (CUS, GAF, JLC), pp. 417–424.
DAC-1985-SpiraH #array #layout: Hardware acceleration of gate array layout (PMS, CH), pp. 359–366.
ICALP-1984-RonRP #csp #implementation #verification: A Hardware Implementation of the CSP Primitives and its Verification (DR, FR, AP), pp. 423–435.
LFP-1984-Brooks #garbage collection #realtime: Trading Data Space for Reduced Time and Code Space in Real-Time Garbage Collection on Stock Hardware (RAB), pp. 256–262.
DAC-1984-Banin #automation #design: Hardware accelerators in the design automation environment (RB), p. 648.
DAC-1984-Dewey: The VHSIC hardware description language (VHDL) program (AD), pp. 556–557.
DAC-1984-GlazierA #logic #named #simulation: Ultimate: A hardware logic simulation engine (MEG, APA), pp. 336–342.
DAC-1984-Lieberherr #standard #towards: Towards a standard hardware description language (KJL), pp. 265–272.
DAC-1984-Milne #verification: A model for hardware description and verification (GJM), pp. 251–257.
DAC-1984-VeigaL #multi #named: HARPA: A hierarchical multi-level hardware description language (PV, ML), pp. 59–65.
ICALP-1983-HalpernMM #semantics: A Hardware Semantics Based on Temporal Intervals (JYH, ZM, BCM), pp. 278–291.
SIGIR-1983-Hollaar #information retrieval: Hardware Systems for Text Information Retrieval (LAH), pp. 3–9.
DAC-1983-Dewey #development: VHSIC hardware description (VHDL) development program (AD), pp. 625–628.
DAC-1983-LieberherrK #named: Zeus: A hardware description language for VLSI (KJL, SEK), pp. 17–23.
DAC-1983-McFarland #behaviour #clustering: Computer-aided partitioning of behavioral hardware descriptions (MCM), pp. 472–478.
DAC-1983-RobinsonD: Programmimg languages for hardware description (PR, JD), pp. 12–16.
DAC-1983-SasakiKOT #logic #named: HAL: A block level HArdware Logic simulator (TS, NK, KO, KT), pp. 150–156.
DAC-1983-UmrigarP #design #realtime #verification: Formal verification of a real-time hardware design (ZDU, VP), pp. 221–227.
ASPLOS-1982-AhujaA #architecture #communication #multi #scheduling: A Multi-Microprocessor Architecture with Hardware Support for Communication and Scheduling (SA, AA), pp. 205–209.
ASPLOS-1982-FusaokaH #compilation #implementation: Compiler Chip: A Hardware Implementation of Compiler (AF, MH), pp. 92–95.
ASPLOS-1982-HennessyJBGG #performance #trade-off: Hardware/Software Tradeoffs for Increased Performance (JLH, NPJ, FB, TRG, JG), pp. 2–11.
ASPLOS-1982-Rattner: Hardware/Software Cooperation in the iAPX-423 (JRR), p. 1.
ASPLOS-1982-Wilkes #implementation #memory management: Hardware Support for Memory Protection: Capability Implementations (MVW), pp. 107–116.
DAC-1982-Adshead #algorithm #complexity #problem #question #scalability #towards: Towards VLSI complexity: The DA algorithm scaling problem: can special DA hardware help? (HGA), pp. 339–344.
DAC-1982-Bruggere: Special purpose vs. general purpose hardware for da (THB), p. 338.
DAC-1982-DammGK #automation: Hardware support for automatic routing (ED, HG, KK), pp. 219–223.
DAC-1982-MaisselO #approach #design #documentation #interactive #simulation #synthesis: Interactive design language: A unified approach to hardware simulation, synthesis and documentation (LIM, DLO), pp. 193–201.
DAC-1982-MaruyamaUKS #design #verification: A verification technique for hardware designs (FM, TU, NK, TS), pp. 832–841.
DAC-1982-Seiler #architecture #design: A hardware assisted design rule check architecture (LS), pp. 232–238.
DAC-1982-TraceyK: A hardware description language for processor based digital systems (JHT, KSK), pp. 330–337.
VLDB-1981-Pramanik: Hardware Organization for Nonnumeric Processing (SP), pp. 66–75.
DAC-1981-BellonSG: Hardware description levels and test for complex circuits (CB, GS, JMG), pp. 213–219.
DAC-1981-NagleP #algorithm #design #multi: Algorithms for multiple-criterion design of microprogrammed control hardware (AWN, ACP), pp. 486–493.
SIGIR-1980-KracsonyKM #analysis #comparative: Comparative Analysis of Hardware Versus Software Text Search (PK, GJK, AM), pp. 268–279.
FM-1979-Berg #design #towards: Towards a Uniform Design Methodology for Software, Firmware, and Hardware (HKB), pp. 1–38.
DAC-1979-Cleemput: Computer hardware description languages and their applications (WMvC), pp. 554–560.
DAC-1979-Darringer #verification: The application of program verification techniques to hardware verification (JAD), pp. 375–381.
DAC-1977-HeathCC #concurrent #development #named: CDL — A tool for concurrent hardware and software development (JRH, BDC, TTC), pp. 445–449.
DAC-1977-Rammig #automation #concept #editing: A concept for the editing of hardware resulting in an automatic hardware-editor (FJR), pp. 187–193.
VLDB-1976-McGregorTD #database #performance: High Performance Hardware for Database Systems (DRM, RGT, WND), pp. 103–116.
DAC-1976-AzemaVD #design #petri net #simulation #verification: Petri nets as a common tool for design verification and hardware simulation (PA, RV, MD), pp. 109–116.
VLDB-1975-HealeyH #architecture #database #scalability: Hardware and System Architecture for a Very Large Database (RH, BH), pp. 520–522.
DAC-1975-RoseA #design #modelling: Modeling and design description of hierarchical hardware/software systems (CWR, MA), pp. 421–430.
SOSP-J-1973-SchroederS72 #architecture #implementation: A Hardware Architecture for Implementing Protection Rings (MDS, JHS), pp. 157–170.
DAC-1971-Sherman #testing: Computer-controlled hardware testing: A programmer’s view of the test center (JWS), pp. 267–272.
SOSP-1971-SchroederS #architecture #implementation: A Hardware Architecture for Implementing Protection Rings (MDS, JHS), pp. 42–54.
DAC-1968-FreemanR #automation #composition #design #named: GENDA — a generalized design automation system for modular hardware (MFF, MR).