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Travelled to:
1 × France
Collaborated with:
J.Rodriguez
Talks about:
signal (1) invert (1) integr (1) simul (1) power (1) model (1) fdsoi (1) empir (1) cmos (1)

Person: Wael Dghais

DBLP DBLP: Dghais:Wael

Contributed to:

DATE 20152015

Wrote 1 papers:

DATE-2015-DghaisR #empirical #modelling #simulation
Empirical modelling of FDSOI CMOS inverter for signal/power integrity simulation (WD, JR), pp. 1555–1558.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.