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Travelled to:
2 × USA
Collaborated with:
C.Sechen M.Vujkovic D.Wadkins
Talks about:
time (3) placement (2) driven (2) standard (1) without (1) circuit (1) effici (1) closur (1) rout (1) larg (1)

Person: William Swartz

DBLP DBLP: Swartz:William

Contributed to:

DAC 20042004
DAC 19951995

Wrote 2 papers:

DAC-2004-VujkovicWSS #performance
Efficient timing closure without timing driven placement and routing (MV, DW, WS, CS), pp. 268–273.
DAC-1995-SwartzS #scalability #standard
Timing Driven Placement for Large Standard Cell Circuits (WS, CS), pp. 211–215.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.